45results about How to "Reduce void defects" patented technology

The application relates to a silicon carbide wafer, a crystal ingot and a preparation method thereof, belonging to the field of semiconductor materials. The silicon carbide single wafer contains nitrogen, and the silicon carbide single wafer has no more than 50 hexagonal color spots, and the sides forming the hexagonal color spots are perpendicular to the <10-10> direction, and each hexagonal color spot The number of cavities contained in the edges is not more than 10. The present application finds that a novel defect existing in a nitrogen-containing silicon carbide wafer is a hexagonal color spot and a void defect existing on the hexagonal color spot, and the hexagonal color spot will make the resistivity of the silicon carbide wafer non-uniform, Seriously affect the electrical properties of semiconductor devices made of silicon carbide wafers, such as making devices made on silicon carbide wafers fail; the existence of voids not only affects the performance of silicon carbide wafers such as breakdown field strength, but the voids may extend to carbonization. A device made from a single wafer of silicon as a substrate. The present application provides a silicon carbide wafer and a silicon carbide ingot containing hexagonal color spots and a small number of voids.

The invention discloses a method for improving gap filling capability of a pre-metal dielectric. The method comprises the following steps: taking a shallow groove isolation area in a semiconductor substrate as a boundary, and forming a CMOS structure adopting a PMOS structure and an NMOS structure, wherein both the PMOS structure and the NMOS structure at least comprise gate oxides and polycrystalline silicon grid electrodes formed on the surface of the semiconductor substrate in sequence, side wall layers positioned on the two sides of the polycrystalline silicon grid electrodes and active areas positioned on the two sides of the polycrystalline silicon grid electrodes and in the semiconductor substrate; depositing a stress silicon nitride layer on the surface of the CMOS structure; depositing a silicon oxide layer on the surface of the stress silicon nitride layer, performing anisotropic etching, and reserving a silicon oxide layer on the side walls of the stress silicon nitride layer; performing fluorine treatment on the surfaces of the silicon oxide layer and the stress silicon nitride layer, and improving the growth selection ratio of the pre-metal dielectric on the surface of the stress silicon nitride layer and the surface of the silicon oxide layer; depositing the pre-metal dielectric. Through the adoption of the method, the defect that void is formed between the grid electrodes can be effectively overcome.

The invention provides a method capable of accurately positioning a coating for producing an anti-counterfeiting optical element and aims at overcoming the defects that the efficiency is low, and fine mapping, metal removal and hollowing cannot be realized in the prior art for producing the anti-counterfeiting element. The method comprises the following steps: forming an undulating structural layer comprising at least a first undulating structural layer area and a second undulating structural layer area on the surface of a substrate, wherein the ratio of the surface area to the apparent area of the first undulating structural layer area is greater than the ratio of the surface area to the apparent area of the second undulating structural layer; forming a first coating on at least one part of the first undulating structural layer area and forming a second coating on at least one part of the second undulating structural layer area; forming protecting layers which can be heated for sublimating on the at least one part of the first coating and on the at least one part of the second coating, wherein the thickness of the protecting layer on the first coating is smaller than that of the protecting layer on the second coating; heating to sublimating the protecting layers until the protecting layer on the first coating is completely sublimated and the protecting layer on the second coating is not completely sublimated; hollowing out the coating part which is not protected by the protecting layers.