Method for improving gap filling capability of pre-metal dielectric

Abstract

The invention discloses a method for improving gap filling capability of a pre-metal dielectric. The method comprises the following steps: taking a shallow groove isolation area in a semiconductor substrate as a boundary, and forming a CMOS structure adopting a PMOS structure and an NMOS structure, wherein both the PMOS structure and the NMOS structure at least comprise gate oxides and polycrystalline silicon grid electrodes formed on the surface of the semiconductor substrate in sequence, side wall layers positioned on the two sides of the polycrystalline silicon grid electrodes and active areas positioned on the two sides of the polycrystalline silicon grid electrodes and in the semiconductor substrate; depositing a stress silicon nitride layer on the surface of the CMOS structure; depositing a silicon oxide layer on the surface of the stress silicon nitride layer, performing anisotropic etching, and reserving a silicon oxide layer on the side walls of the stress silicon nitride layer; performing fluorine treatment on the surfaces of the silicon oxide layer and the stress silicon nitride layer, and improving the growth selection ratio of the pre-metal dielectric on the surface of the stress silicon nitride layer and the surface of the silicon oxide layer; depositing the pre-metal dielectric. Through the adoption of the method, the defect that void is formed between the grid electrodes can be effectively overcome.

Description

Technical field [0001] The present invention relates to the manufacturing technology of semiconductor devices, and in particular to a method for improving the gap filling capability of a dielectric pre-metal layer (PMD). Background technique [0002] Currently, when manufacturing semiconductor devices, silicon nitride can be used to induce stress in the transistor channel, thereby adjusting the carrier mobility in the channel. Complementary Metal-Oxide-Semiconductor (CMOS) structures include NMOS structures and PMOS structures. The manufacturing method of the CMOS structure in the prior art, combined with its specific cross-sectional structure diagram, Figure 1a to Figure 1c Be explained. [0003] See Figure 1a , A semiconductor substrate 100 is provided, a shallow trench isolation region (STI) 101 is formed on the semiconductor substrate 100, and a PMOS structure and an NMOS structure are formed on both sides of the STI 101 on the semiconductor substrate 100; specifically: [0004...

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Problems solved by technology

[0009] It should be noted that for the rapidly developing sub-micron semiconductor devices, the distance between the gate and the gate is very narrow, mostly less than 10 nanometers, so in the previous step: the area between the gate and the gate When depositing the pre-metal dielectric layer, it is easy to cause uneven material filling and void defects. The void leads to the passage between the gate and the gate. If the conductive metal is filled inside, the conductive metal will just fill in the passage between the gate and the gate caused by the void, so that the gate and the gate are connected, and finally the semiconductor device will fail.

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