88results about How to "Improve defect density" patented technology

The invention relates to a method for increasing the uniformity of on-chip n-type doping concentration of a silicon carbide epitaxial wafer. According to the method, a chemical vapor deposition growth technology serves as basis; a silicon surface silicon carbide substrate with the deviation (11-20) direction of 4 degrees or 8 degrees is adopted; silane and propane serve as growth sources; hydrogen chloride serves as an auxiliary gas for inhibiting gas phase nucleation of a silicon component; hydrogen serves as a carrier gas and a diluent gas; nitrogen serves as an n-type doping agent. A small amount of process gas silane or propane is added into a base air floatation gas and is pushed by the air floatation gas serving as a carrier gas to the edge of the substrate to finely adjust the carbon silicon ratio of the edge of the substrate, so that the doping efficiency of the n-type doping source on the edge of the substrate is changed, the doping concentration deviation of the edge point and the central point of the epitaxial wafer caused by non-linear exhausting is effectively reduced, and the uniformity of the on-chip doping concentration of the epitaxial wafer is effectively optimized on the premise of not changing key process parameters. The selection window of the key process parameters is enlarged and technical support is provided for the growth of a high-quality silicon carbide epitaxial material.

An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.

The invention discloses a method for improving the uniformity of p-type doping concentration in a silicon carbide epitaxial wafer. Based on a chemical vapor deposition growth technique, a small amountof silicon source, carbon source, hydrogen chloride, trimethylaluminum and the like are added into a substrate air-floating gas, and then a small amount of process gas is pushed to an edge of a graphite substrate by taking the air-floating gas as a carrier gas, so that the p-type doping efficiency of the edge of the substrate is finely adjusted. By adopting the method, the deviation of the dopingconcentration of an edge point and a center point caused by nonlinear depletion of the epitaxial wafer is effectively reduced, and the uniformity of the intra-wafer doping concentration of the epitaxial wafer is effectively optimized without changing key process parameters. The process is compatible with conventional SiC epitaxial processes, and has a relatively high promotion value.

Disclosed is a process for producing a silicon carbide epitaxial wafer which has extremely superior surface flatness and has extremely low densities of carrot defects and triangular defects that usually appear after the occurrence of epitaxial growth. The silicon carbide epitaxial wafer can be produced through: a first step of annealing a silicon carbide bulk substrate that has a tilt angle against the face <0001> of smaller than 5 degrees in a reduction gas atmosphere at a first temperature (T1) for a treatment time (t); a second step of decreasing the temperature of the substrate in a reduction gas atmosphere; and a third step of supplying at least a gas containing silicon atoms and a gas containing carbon atoms at a second temperature (T2) that is lower than the annealing temperature (T1) employed in the first step to cause epitaxial growth.

This invention provides a process for growing Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaxial layers by using metal organic chemical vapor deposition (MOCVD).The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaxial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si01.Ge0.9 due to the large mismatch between this layer and Si substrate.Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and / or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaxial layers.Finally, a GaAs epitaxial layer is grown on said Ge film by using MOCVD.

This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and / or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.

An annealing method to reduce defects of epitaxial films and epitaxial films formed therewith. The annealing method includes features as follows: apply a pressure ranged from 10 MPa to 6,000 MPa to an epitaxial film grown on a substrate through a vapor phase deposition process and heat the epitaxial film at a temperature lower than the melting temperature of the epitaxial film. Through applying pressure to the epitaxial film, the lattice strain of the epitaxial film is alleviated, and therefore the defect density of the epitaxial film also decreases.

In a manufacturing process of a display device, hydrogenation in an I layer of photodiodes D1 and D2 is progressed less than that in a channel portion of a pixel TFT, and a defect density due to dangling bonds not terminated in the I layer of the photodiodes D1 and D2 is made higher than a defect density in the channel portion of the pixel TFT. Thus, while suppressing a leakage current of the pixel TFT, the sensitivity of the photodiodes D1 and D2 to light is improved. Moreover, a gate electrode is provided above an i region of a pin-type optical sensor diode with an insulating film interposed therebetween. Thus, a gate voltage can control a threshold of a bias voltage when a current starts to flow into the optical sensor diode and a leakage current is prevented from flowing into the optical sensor diode.

The invention discloses a crystal growth furnace for preparing single crystals through a PVT method and an application of the crystal growth furnace, which belong to the field of semiconductor material preparation. The crystal growth furnace for preparing the single crystals by the PVT method comprises a crucible, a heat preservation structure, a furnace body and a heating coil which are arrangedfrom inside to outside, and further comprises a seed crystal column arranged in the crucible. The side wall of the crucible comprises an interlayer, the interlayer comprises an inner side wall and anouter side wall, the porosity of the inner side wall is higher than that of the outer side wall, and the interlayer forms a raw material cavity; the extension directions of the seed crystal column andthe central axis of the crucible are approximately the same, and a crystal growth cavity is formed between the seed crystal column and the inner surface of the inner side wall; the heating coil induces and heats the side wall of the crucible, so that the raw materials in the raw material cavity penetrate through the inner side wall after sublimation, and are conveyed to the surface of the seed crystal column in the crystal growth cavity along the radial gas phase for crystal growth. The crystal growth furnace can be used for efficiently and quickly preparing the silicon carbide single crystalwith extremely low defect density and the substrate of the silicon carbide single crystal, so that a technical foundation is laid for large-scale commercialization of high-quality and low-cost silicon carbide substrates.

A method and structure for producing lasers having good optical wavefront characteristics, such as are needed for optical storage includes providing a laser wherein an output beam emerging from the laser front facet is essentially unobstructed by the edges of the semiconductor chip in order to prevent detrimental beam distortions. The semiconductor laser structure is epitaxially grown on a substrate with at least a lower cladding layer, an active layer, an upper cladding layer, and a contact layer. Dry etching through a lithographically defined mask produces a laser mesa of length lc and width bm. Another sequence of lithography and etching is used to form a ridge structure with width w on top of the mesa. The etching step also forming mirrors, or facets, on the ends of the laser waveguide structures. The length ls and width bs of the chip can be selected as convenient values equal to or longer than the waveguide length lc and mesa width bm, respectively. The waveguide length and width are selected so that for a given defect density D, the yield YD is larger than 50%.

The invention relates to a three-dimensional porous graphene-based electrochemical electrode material, a preparation and application thereof. Three-dimensional porous graphene is prepared by hydrothermal method, and has abundant three-dimensional micron-pores and two-dimensional in-plane nanopores, the three-dimensional porous graphene-based electrochemical electrode material is obtained by: adding a suspension of the above graphene dropwise to the center of a substrate, and conducting vacuum pumping and drying at room temperature. The three-dimensional porous graphene-based electrochemical electrode material provided by the invention can be applied to electrochemical sensors to detect the content of ascorbic acid, uric acid or nitrite, and has the advantages of high sensitivity, short response time, strong anti-interference ability, good repeatability, good long-term stability and high recovery rate.