22403results about "Printed circuit assembling" patented technology

Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input / output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.

Memory Cards containing Integrated Circuits and other electronic components (e.g. resistors) in a variety of form factors having high quality external surfaces of polycarbonate, synthetic paper (e.g. Teslin), or other suitable material (e.g. PVC) can be made through use of injection molded thermoplastic material or thermosetting material that becomes the core layer of said Memory Cards and similar devices. The object of the invention is to provide the following properties to Memory Cards: rapid production cycle, high volume manufacturing throughput, security, electronics protection, better tamper resistance, durability, and highly reliable complex electronics encapsulation, achieved through a process utilizing low temperature and low pressure.

Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and / or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and / or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Provided are a stretchable electric circuit and a manufacturing method thereof The method for manufacturing the stretchable electric circuit includes forming a mold substrate, forming a stretchable substrate having a first flat surface and a first corrugated surface outside the first flat surface on the mold substrate, removing the mold substrate, forming a corrugated wire on the first corrugated surface, and forming an electric device connected to the corrugated wire on the first flat surface.

A computer subassembly aspect is disclosed comprising a case defining an interior, a primary circuit board located in the interior of the case, and a BIOS chip socket mounted on the primary circuit board. The case has an opening formed therein that is aligned with a position of the BIOS chip socket on the primary circuit board to permit insertion of a BIOS chip into the BIOS chip socket through the opening. A method of assembling a computer is also disclosed that comprises assembling a subassembly of a laptop computer in a first location, with the subassembly including a BIOS chip socket for receiving a BIOS chip but lacking a BIOS chip, transporting the subassembly from the first location to a second location, and installing a BIOS chip into the BIOS chip socket of the subassembly when the subassembly is in the second location.