29178results about "Semiconductor/solid-state device testing/measurement" patented technology

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

A disc-type unit 10 adjusts temperature of a control face 14 by means of a heater 12 and coolant, with a hollow plate 11 to which the heater 12 is secured, a cavity 13 formed in the hollow plate 11 and a piping 20 for supplying the coolant to the cavity 13, the piping 20 opening in the cavity 13, and the coolant being jetted to a portion to which the heater 12 is secured or a portion in proximity thereto and which shows high temperature rise when energizing the heater 12.

A method for managing UV irradiation for curing a semiconductor substrate, includes: passing UV light through a transmission glass window provided in a chamber for curing a semiconductor substrate placed in the chamber; monitoring an illuminance upstream of the transmission glass window and an illuminance downstream of the transmission glass window; determining a timing and / or duration of cleaning of the transmission glass window, a timing of replacing the transmission glass window, a timing of replacing a UV lamp, and / or an output of the UV light based on the monitored illuminances.

Alignment accuracy between two or more patterned layers is measured using a metrology target comprising substantially overlapping diffraction gratings formed in a test area of the layers being tested. An optical instrument illuminates all or part of the target area and measures the optical response. The instrument can measure transmission, reflectance, and / or ellipsometric parameters as a function of wavelength, polar angle of incidence, azimuthal angle of incidence, and / or polarization of the illumination and detected light. Overlay error or offset between those layers containing the test gratings is determined by a processor programmed to calculate an optical response for a set of parameters that include overlay error, using a model that accounts for diffraction by the gratings and interaction of the gratings with each others' diffracted field. The model parameters might also take account of manufactured asymmetries. The calculation may involve interpolation of pre-computed entries from a database accessible to the processor. The calculated and measured responses are iteratively compared and the model parameters changed to minimize the difference.

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.