6354 results about "Device form" patented technology

The present invention relates to a tubular suture reinforcement material suitable for use in automatic suturing devices that are widely used in surgical operations, etc. More specifically, the present invention relates to a tubular suture reinforcement material with which a tubular shape is easily obtained to thereby increase its productivity, and removal of thread is easily achieved. The present invention provides a tubular suture reinforcement material for an automatic suturing device formed by stacking two sheet-like materials and sewing together both ends of the two sheet-like materials using two chain stitches (intralooping stitches) each thread end at each sewing end is suitably extended, and the thread end is passed through an anterior loop continuous to the thread end, thereby preventing the thread from unraveling.

A semi-insulating bulk single crystal of silicon carbide is disclosed that has a resistivity of at least 5000 OMEGA-cm at room temperature and a concentration of deep level trapping elements that is below the amounts that will affect the resistivity of the crystal, preferably below detectable levels. A method of forming the crystal is also disclosed, along with some resulting devices that take advantage of the microwave frequency capabilities of devices formed using substrates according to the invention.

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical characteristic, such as the number of series-connected devices forming the NAND string, but both groups are disposed in a region of the memory array traversed by a plurality of global array lines. The memory array may include a three-dimensional memory array having more than one memory plane. Some of the NAND strings of the first group may be disposed on one memory plane, and some of the NAND strings of the second group may be disposed on another memory plane. In some cases, NAND strings of both groups may share global array lines.

An anastomosis device formed from a Shape Memory Alloy (SME) wire that is annealed into a tight coil (e.g., flat coil, helical coil, cylindrical coil) that is subsequently substantially straightened (e.g., straight, longitudinally stretched spring-like shape) for being constrained within an elongate member of an anastomosis introducer instrument. After positioning and holding two tissue walls of adjacent lumens into apposition with a distally presented grasper of the instrument, a piercing tip of the anastomosis device is dispensed and inserted through the tissue walls before being allowed to relax to its tight coil shape, thereby forming the anastomosis attachment. The anastomosis device is released from the anastomosis introducer instrument, such as by fully dispensing its proximal end. Thereby, efficient single lumen anastomosis of gastrointestinal, bilatory, or other vessels may be achieved with a minimum of laparoscopic punctures, or perhaps performed fully as an endoscopic procedure.

Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

Devices formed of or including biocompatible polyhydroxyalkanoates are provided with controlled degradation rates, preferably less than one year under physiological conditions. Preferred devices include sutures, suture fasteners, meniscus repair devices, rivets, tacks, staples, screws (including interference screws), bone plates and bone plating systems, surgical mesh, repair patches, slings, cardiovascular patches, orthopedic pins (including bone filling augmentation material), adhesion barriers, stents, guided tissue repair / regeneration devices, articular cartilage repair devices, nerve guides, tendon repair devices, atrial septal defect repair devices, pericardial patches, bulking and filling agents, vein valves, bone marrow scaffolds, meniscus regeneration devices, ligament and tendon grafts, ocular cell implants, spinal fusion cages, skin substitutes, dural substitutes, bone graft substitutes, bone dowels, wound dressings, and hemostats. The polyhydroxyalkanoates can contain additives, be formed of mixtures of monomers or include pendant groups or modifications in their backbones, or can be chemically modified, all to alter the degradation rates. The polyhydroxyalkanoate compositions also provide favorable mechanical properties, biocompatibility, and degradation times within desirable time frames under physiological conditions.

Embodiments of the invention provide processes to form a high quality contact level connection to devices formed on a substrate. In one embodiment, a method for depositing a material on a substrate is provided which includes exposing the substrate to a buffered oxide etch solution to form a silicon hydride layer during a pretreatment process, depositing a metal silicide layer on the substrate, and depositing a first metal layer (e.g., tungsten) on the metal silicide layer. The buffered oxide etch solution may contain hydrogen fluoride and an alkanolamine compound, such as ethanolamine diethanolamine, or triethanolamine. The metal silicide layer may contain cobalt, nickel, or tungsten and may be deposited by an electroless deposition process. In one example, the substrate is exposed to an electroless deposition solution containing a solvent and a complexed metal compound.

A substrate under tension and / or compression improves performance of devices fabricated therein. Tension and / or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.