6276 results about "Passivation" patented technology

Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.

PCT No. PCT/US95/13325 Sec. 371 Date Sep. 28, 1997 Sec. 102(e) Date Sep. 28, 1997 PCT Filed Oct. 10, 1995 PCT Pub. No. WO96/12316 PCT Pub. Date Apr. 25, 1996Fuel cell stacks comprising stacked separator/membrane electrode assembly fuel cells in which the separators comprise a series of thin sheet platelets, having individually configured serpentine micro-channel reactant gas humidification active areas and cooling fields therein. The individual platelets are stacked with coordinate features aligned in contact with adjacent platelets and bonded to form a monolithic separator. Post-bonding processing includes passivation, such as nitriding. Preferred platelet material is 4-25 mil Ti, in which the features, serpentine channels, tabs, lands, vias, manifolds and holes, are formed by chemical and laser etching, cutting, pressing or embossing, with combinations of depth and through etching preferred. The platelet manufacturing process is continuous and fast. By employing CAD based platelet design and photolithography, rapid change in feature design can accommodate a wide range of thermal management and humidification techniques. One hundred H2-O2/PEM fuel cell stacks of this IFMT platelet design will exhibit outputs on the order of 0.75 kW/kg, some 3-6 times greater than the current graphite plate PEM stacks.

Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

The invention belongs to the technical field of nanometer biological materials, and particularly relates to an 800nm excitation-based up/down conversion dual-mode fluorescent nanomaterial for Nd<3+> sensitization and a synthesis method thereof. The synthetic up/down conversion dual-mode fluorescent nanomaterial for Nd<3+>sensitization designed by the invention has a multi-layer core-shell structure, and comprises a down conversion luminous layer, an up conversion luminous layer, an isolation layer and a passivation layer. Different layers of the material synergistically play respective different roles, and meanwhile, the dual-mode fluorescent probe with up conversion fluorescence and down conversion fluorescence is finally achieved under an 800nm of excitation light with a low-heat effect. The up conversion excitation light is expanded to about 800nm from 980nm by Nd<3+>, Yb<3+> and Er<3+>-doped NaGdF4:Nd, Yb, Er up conversion layer due to introduction of Nd<3+>, and the fluorescent process from a near infrared light to a visible light is achieved. The process meets the requirements of an in-vitro fluorescent probe. In addition, the typical down conversion fluorescence from the near infrared light to a far infrared light is also achieved in one nanoparticle due to the synergistic effect of the NaGdF4:Nd core.

A process for fabricating an electronic device structure on or in a substrate. A storage and dispensing vessel is provided, containing a solid-phase physical sorbent medium having physically adsorbed thereon a fluid for fabrication of the electronic device structure, e.g., a source fluid for a material constituent of the electronic device structure, or a reagent such as an etchant or mask material which is utilized in the fabrication of the electronic device structure but does not compose or form a material constituent of the electronic device structure. In the process, the source fluid is desorbed from the physical sorbent medium and dispensing source fluid from the storage and dispensing vessel, and contacted with the substrate, under conditions effective to utilize the material constituent on or in the substrate. The contacting step of the process may include process steps such as ion implantation; epitaxial growth; plasma etching; reactive ion etching; metallization; physical vapor deposition; chemical vapor deposition; cleaning; doping; etc. The process of the invention may be employed to fabricate electronic device structures such as transistors; capacitors; resistors; memory cells; dielectric material; buried doped substrate regions; metallization layers; channel stop layers; source layers; gate layers; drain layers; oxide layers; field emitter elements; passivation layers; interconnects; polycides; electrodes; trench structures; ion implanted material layers; via plugs; precursor structures for the foregoing electronic device structures; and device assemblies comprising more than one of the foregoing electronic device structures. The electronic device structure fabricated by such process may in turn may be employed as a component of an electronic product such as a telecommunications device or electronic appliance.

The invention discloses a multilayer silicon nitride antireflection film of a crystalline silicon solar cell and a preparation method of the multilayer silicon nitride antireflection film, belonging to the technical field of manufacturing of semiconductor crystalline silicon and solar cells. The multilayer silicon nitride antireflection film comprises at least three silicon nitride films which are deposited on a silicon substrate, the refraction indexes of all the silicon nitride films are sequentially reduced from bottom to top, and the thicknesses of all the silicon nitride films are sequentially increased from bottom to top. According to the invention, the passivation effect of a coating film is effectively improved, the antireflection effect of the antireflection film is improved, thepassivation effect of the antireflection film is enhanced, and the photoelectric conversion efficiency of the solar cell is increased.