16512 results about "Engineering physics" patented technology

First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.

Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.

Methods for forming compositions comprising a single-phase rare-earth dielectric disposed on a substrate are disclosed. In some embodiments, the method forms a semiconductor-on-insulator structure. Compositions and structures that are formed via the method provide the basis for forming high-performance devices and circuits.

A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.

A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.

In embodiments of the present invention, a method and system is provided for designing improved intelligent, LED-based lighting systems. The LED based lighting systems may include fixtures with one or more of rotatable LED light bars, integrated sensors, onboard intelligence to receive signals from the LED light bars and control the LED light bars, and a mesh network connectivity to other fixtures.

Devices are provided for the controlled exposure or release of contents stored in hermetically sealed reservoirs. The devices comprise a primary substrate having a front side and a back side, and including one or more hermetic sealing materials; a plurality of reservoirs in the primary substrate positioned between the front side and the back side; reservoir contents, which comprise chemical molecules (such as drugs) or a secondary device (such as a glucose sensor), located inside the reservoirs; a hermetic sealing substrate having a surface composed of one or more hermetic sealing materials; and a hermetic seal formed between and joining the primary substrate and the hermetic sealing substrate, wherein the hermetic seal independently seals the reservoirs.

An electronic cigarette device includes electronic cigarette and a case for accommodating electronic cigarette. The case has a first magnetic part at a position coupled to electronic cigarette, the electronic cigarette correspondingly has a second magnetic part absorbing the first magnetic part to keep the electronic cigarette and the case firmly engaged. The case has a first connector at a position coupled to electronic cigarette, the first connector comprises a first socket, a first pole in center of the first socket, and first insulating bush inserted between the first socket and first pole. The electronic cigarette includes an inhaling shell and a power shell, the power shell has a battery therein, one end of the power shell has a second connector connected with a second battery and coupled to the first connector. The electronic cigarette device is convenient for placing electronic cigarette into the case or taking it out therefrom.

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Briefly described, the invention provides a photovoltaic assembly power output utilizing device which partially charges a capacitor assembly. This capacitor assembly is then partially discharged by a DC/DC power converter in different ranges of voltages in which the power output from the photovoltaic assembly peaks for different light intensities.

A susceptor for supporting a semiconductor wafer during deposition of a layer on a front side of the semiconductor wafer, the semiconductor wafer having a diameter D and, at its edge, a notch having a depth T, comprising:

• • a ring-shaped placement area having an internal diameter d for the placement of the semiconductor wafer in the edge region of a rear side of the semiconductor wafer, wherein, with the semiconductor wafer having been placed, the relationship (D−d)/2<T is satisfied; and
  • a protrusion of the area for the placement of semiconductor wafer in the region of the notch of the semiconductor wafer extending the placement area inward, and which completely underlays the notch of the semiconductor wafer.

A portfolio-style protective cover for portable electronic devices is disclosed.

A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite the front surface. A plurality of through holes extend from the bottom surface of the cap member to the top surface. The capped chip assembly further includes a plurality of metallic interconnects extending from the bond pads at least partially through the through holes, the metallic interconnects including stud bumps joined to the bond pads, the stud bumps contacting and engaging at least one of (i) the top surface of the cap member surrounding the through holes and (ii) inner surfaces of the through holes.

The present invention relates to a high efficiency three-level inverter apparatus containing both bipolar and field effect transistors. An embodiment of a modified control scheme is also presented whereby transistors are modulated differently for each quadrant of output voltage-current phase. This embodiment of a modified control scheme allows efficient switching of field effect transistors without additional freewheeling and series diodes.