A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power,
noise, etc.), which will be then implemented as a
standard cell (also known hereafter as metacell), from a set of post-
layout patterns. A post-
layout pattern represents a part or whole of a
standard cell and contains information regarding the pattern including, but not limited to,
layout, timing, area, power and
noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic
library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to
standard cell-based design methodology.