901results about How to "Reduce chip area" patented technology

System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

A pixel circuit, and a method for operating a high-low sensitivity (HLS) pixel circuit, to provide increased dynamic range in an imager. The pixel circuit combines a four transistor (“4T”) and a three-transistor plus capacitor (“3TC”) configuration in one pixel, where the 4T portion of the pixel is coupled to a high sensitivity buried photodiode region, and the 3TC portion of the pixel is coupled to a low sensitivity buried photodiode region. The pixel circuit first reads out charge from the high sensitivity photodiode region and compares it to a reset voltage, then reads out charge from the low sensitivity photodiode region. Under an alternate embodiment, multiple HLS pixels are coupled through a common floating diffusion node.

A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.

An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.

A slow-wave transmission line component having a slow-wave structure. The slow-wave structure includes a floating shield employing one of electric and magnetic induction to set a potential on floating strips of said floating shield to about 0, thereby reducing losses caused by electric coupling to a substrate. A spacing between the strips is small to inhibit electric field from passing the metal strips to the substrate material.

A semiconductor integrated circuit device includes a HFET formed on part of a substrate made of sapphire and including a Group III-V nitride semiconductor layer, a dielectric film formed on the substrate to cover the top and side surfaces and upper corners of the Group III-V nitride semiconductor layer, a microstrip line formed with the dielectric film interposed between the substrate and the microstrip line, and a drain lead which is formed on part of the dielectric film and through which the HFET is electrically connected to the microstrip line.

A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided.

A light emitting diode device emitting at a wavelength of 390-415 nm has a bulk gallium and nitrogen containing substrate with an active region. The device has a current density of greater than about 175 Amps / cm2 and an external quantum efficiency with a roll off of less than about 5% absolute efficiency.

A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

A switched-capacitor regulator is provided for regulating the output voltage of a voltage supply. The switched-capacitor regulator includes a supply input terminal capable of receiving a supply voltage, two or more flying capacitors, a regulation switch located between each flying capacitor and the supply input terminal, and a voltage control circuit. The activity of the regulation switches is controlled by the voltage control circuit. In one embodiment of the invention, the voltage control circuit includes a feedback resistance area having one or more feedback resistors located between the output of the flying capacitors and a ground terminal, a first gain stage connected to the feedback resistance area, and two or more second switchable gain stages, which are each connected to a regulation switch and the first gain stage. The switched-capacitor regulator operates in pseudo-continuous regulator mode using three-stage switchable operational amplifiers with time-multiplexed pole-splitting compensation.

An image sensing apparatus comprises a pixel including, a column signal line, a readout circuit, an output line, and an output unit. The readout circuit includes a first accumulation unit, a first opening / closing unit, a second accumulation unit, a transmission unit, and a second opening / closing unit. A capacitance of the first accumulation unit is smaller than a capacitance of the second accumulation unit, and the signal held by the second accumulation unit is read out to the output unit based on the capacitance of the second accumulation unit and the capacitance of the output line.

In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.

The invention relates to a power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of a novel groove structure and a manufacture method thereof. The unit cell of the element zone of the power MOSFET device adopts groove structure; an insulating oxide layer is arranged in the unit cell groove; the thickness of a second isolated gate oxide layer in the unit cell groove is more thanthe thickness of a first isolated gate oxide layer; conductive polysilicon is deposited in the cell unit groove; the extending distance of the first conductive polysilicon is more than the extending distance of the second conductive polysilicon in the unit cell groove; the groove mouth of the unit cell groove is covered by an insulating medium layer; a source electrode contact hole is filled withsecond contract hole filling metal; the second contract hole filling metal, a first conductive type filling zone and a second conductive type layer are in ohmic contact; source electrode metal is arranged above the unit cell groove; the source electrode metal and the second contact hole filling metal are electrically connected; and the first conductive polysilicon, the source electrode metal and the like are in potential connection. The power MOSFET device has the advantages of low conduction resistance, small grid leak electric charge Qgd, low switching speed, low switching loss, simple technology and low cost.