3815 results about "Field effect" patented technology

A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.

Provided is a Schottky barrier nanowire field effect transistor, which has source / drain electrodes formed of metal silicide and a channel formed of a nanowire, and a method for fabricating the same. The Schottky barrier nanowire field effect transistor includes: a channel suspended over a substrate and including a nanowire; metal silicide source / drain electrodes electrically connected to both ends of the channel over the substrate; a gate electrode disposed to surround the channel; and a gate insulation layer disposed between the channel and the gate electrode.

A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and / or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.

A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10−18 / cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

The present invention relates to a programmable semiconductor device, preferably a FinFET or tri-gate structure, that contains a first contact element, a second contact element, and at least one fin-shaped fusible link region coupled between the first and second contact elements. The second contact element is laterally spaced apart from the first contact element, and the fin-shaped fusible link region has a vertically notched section. A programming current flowing through the fin-shaped fusible link region causes either significant resistance increase or formation of an electric discontinuity in the vertically notched section. Alternatively, the vertically notched section may contain a dielectric material, and application of a programming voltage between a gate electrode overlaying the vertically notched section and one of the contact elements breaks down the dielectric material and allows current flow between the gate electrode and the fin-shaped fusible link region.

An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source / drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S / D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.

A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1 / f noise. The channel-junction IGFET is normally fabricated to be of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. A p-channel surface-channel IGFET (102 or 162), which is typically fabricated to be of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically fabricated to be of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and / or minimize implant-induced amorphization (a potential problem for source / drain (S / D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S / D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S / D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

The present invention provides a thin film field-effect transistor comprising a substrate having thereon at least a gate electrode, a gate insulating film, an active layer, a source electrode, and a drain electrode, wherein the active layer is an oxide semiconductor layer, a resistance layer having an electric conductivity that is lower than an electric conductivity of the active layer is provided between the active layer and at least one of the source electrode or the drain electrode, and an intermediate layer comprising an oxide comprising an element having a stronger bonding force with respect to oxygen than that of the oxide semiconductor in the active layer is provided between the active layer and the resistance layer.

A lighting device (132) includes a circuit having a power supply and a plurality of light emitting diodes (120) connected in series with the power supply. The plurality of light emitting diodes (120) includes at least two groups of series-connected light emitting diodes, the groups of series-connected light emitting diodes being connected in series. A different optically isolated field effect transistor (U3-U5) is connected in parallel with each group of series-connected light emitting diodes, for selectively shunting around the group of series-connected light emitting diodes. A different capacitor (C8-C10) can also be connected in parallel with each group of series-connected light emitting diodes. A controller (U2) is connected to a gate of each of the optically isolated field effect transistors (U3-U5) for selectively turning the optically isolated field effect transistors (U3-U5) on and off. Thus, the controller U2 is electrically isolated from the power supply by the optically isolated field effect transistors (U3-U5). The light emitting diodes (120) can be driven and controlled using pulse width modulation methods.

A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.

A SOI-structure MOS field-effect transistor. In this transistor, agate electrode and a p- region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p- region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

A TFT is provided which includes, on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode, wherein a carrier concentration of the active layer is 3×1017 cm−3 or more and a film thickness of the active layer is 0.5 nm or more and less than 10 nm. A TFT is provided which has a low OFF current and a high ON-OFF ratio, and is improved in environmental temperature dependency. Also, a display using the TFT is provided.