853results about "Amplififers with field-effect devices" patented technology

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and / or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

Methods and apparatus are provided for substantially reducing and / or canceling nonlinearities of any order in circuits, devices, and systems such as amplifiers and mixers. In particular, methods and apparatus are provided for substantially reducing and / or canceling third order nonlinearities in circuits, devices, and systems such as amplifiers and mixers. A first coupler is used to split an input signal into two equal-amplitude in-phase components, each component is processed by two nonlinear devices with different nonlinearities, and a final combiner, such as a 180-degree hybrid, recombines the processed signals 180 degrees out of phase and substantially reduces and / or cancels the undesired nonlinear distortion components arising due to nonlinearities in the nonlinear devices.

The present invention relates to a preamplifier suitable for use with Electret Condenser Microphones such as used within telecommunication equipment. More particularly the invention relates to a preamplifier specially suited for the demands to such a preamplifier within telecommunication equipment: low input capacitance, gain and a combined terminal for output and supply voltage, thus making the preamplifier suitable for two terminal microphone assemblies. These features are obtained with a two stage amplifier with a first stage optimised for low input capacitance and the second stage being able to provide gain. The preamplifier may be implemented using an ASIC, thus making the preamplifier suitable for applications with very limited space available, such as for integration within microphone assemblies.

An amplifying apparatus amplifies an input signal supplied to an input terminal and outputs an output signal from an output terminal. The apparatus includes a high-potential power supply line through which a high voltage is supplied; a low-potential power supply line through which a low voltage is supplied; a control unit; and a power supply in which one of the high and low voltages is a fixed voltage, and which generates, as the other of the high and low voltages, one of a first voltage in which a polarity of the fixed voltage is inverted, and a second voltage which is closer to the ground potential than the first voltage is. The control unit controls the power supply to cause the other of the high and low voltages to be switched between the first voltage and the second voltage in accordance with a signal level of the output signal.

The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.

A high efficiency modulating RF amplifier (10) for amplitude modulating a signal defined by a phase information signal (1) and an envelope signal (2) comprises a power supply (30) arranged to provide an operating voltage under control of the envelope signal (2). The power supply (30) comprises a plurality of power supply stages (40) and a plurality of supply switches (50) coupled between the plurality of power supply stages (40) and the modulator (20). The power supply (30) is arranged to select one of the power supply stages (40) to provide the operating voltage under control of the envelope signal (2). The high efficiency modulator RF amplifier further comprises a modulator (20) for receiving the phase information signal (1), the envelope signal (2) and the operating voltage. The modulator (20) is arranged to provide an output signal of which an amplitude is modulated under control of the envelope signal (2).

An amplification unit comprising a signal splitter operable to split an input signal into a first signal and a second signal such that the two resulting signal portions are in quadrature, a main driver operable to create a third signal from the first signal, and a main amplifier operable to amplify the first driver signal. Amplification unit also may include an auxiliary driver capable of creating a fourth signal from the second signal, an auxiliary amplifier capable of amplifying the second signal, a bias control component operable to control at least part of the output of the auxiliary amplifier, and a signal combiner operable to combine the third signal and the fourth signal and realigning the phase of the third signal and fourth signal. In some embodiments enhanced amplification unit is a Doherty-type amplifier.

A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.

A power amplifier (PA) adjustably operable between two classes of operation. The range of operation lies in a range of operation between a conventional, linear, conjugately matched Class AB characteristic amplifier and a higher efficiency switching Class E characteristic amplifier. A circuit topology having a push-pull configuration that allows a Class E characteristic of operation.

A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

A FET amplifier which minimizes the worsening of the distortion-susceptibility due to variations in the ambient temperature of operation is to be provided. An LDMOS FET 1, whose source terminal is grounded and to which are applied a gate voltage Vgs from a gate bias terminal 3 via a temperature-compensating circuit 2 and a choke coil and a drain voltage Vds from a drain bias terminal 4 via a choke coil operates as a source-grounded type amplifier. In the temperature compensating circuit 2, the resistances of fixed resistance elements 21 and 22 connected in parallel are set to be the same or have the same number of digits, and those of thermosensitive resistance elements (thermistors) 23 and 24 are set to be a combination of a value greater by one digit and a value smaller by one digit than that of the fixed resistance element 21 or the fixed resistance element 22 at the standard level (+25° C.) in the ambient temperature range of operation.

A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and / or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity.

A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a power supply voltage terminal. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the control electrode of the first power transistor and the power supply voltage terminal. The first decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

A power amplifier circuit includes: a transformer receiving a first signal and generating a transformed signal from the first signal; and a transistor receiving a second signal having a direct current (DC) component, and generating an output signal. The second signal and the transformed signal are mixed, via a terminal connected with the transformed signal, wherein an envelope of the output signal is controlled by the first signal.

An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier. In addition, the power amplifier can further include at least one peaking amplifier connected in parallel with the carrier amplifier; a first differential combining structure, where the first combining structure includes a first plurality of quarter wave transformers that are configured to combine respective first differential outputs of the carrier amplifier in phase to generate a first single-ended output signal, and a second differential combining structure, where the second combining structures includes a second plurality of quarter wave transformers that are configured to combine respective second differential outputs of the at least one peaking amplifier in phase to generate a second single-ended output signal, where the first single-ended output signal and the second single-ended output signal are combinable in-phase to provide an overall output.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units. The unit cells are disposed in linear arrays so that the transistor device units are disposed in linear arrays and the capacitors are disposed in linear arrays.

A transmitter circuit for use in a display device of the type having a transmission line consisting of aluminum or copper conductor formed on a glass substrate includes a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting and inverting output terminals; and an output-waveform control circuit for detecting the edge of the waveform of the input signal and responding by increasing the signal current temporarily.

The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

The invention discloses a low-voltage difference voltage adjuster, belonging to the technical field of an electronic circuit. The low-voltage difference voltage adjuster comprises an error amplifier,an output amplifier and a frequency compensating circuit, wherein the error amplifier is a first-class folding cascode amplifier, the output amplifier is coupled with the error amplifier, receives control voltage and comprises a transistor and two divider resistors which are connected in series; the frequency compensating circuit is respectively coupled with the error amplifier and the output amplifier; and the frequency compensating circuit comprises a voltage-controlling current source circuit consisting of at least one transistor and at least one compensating capacitor coupled with the voltage-controlling current source circuit. The low-voltage difference voltage adjuster can solves the problems that the current voltage adjuster has larger compensating capacitance and can not carry outon-chip integration, can provide complete chip integration, has good voltage-suppression specific characteristic, reduce the number of the compensating capacitance and simplify the compensating circuit.

An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.