1301 results about "Low input" patented technology

A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input / output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input / output lines connected to the local input / output line sense amplifier in response to a column selection signal, and a local input / output line precharging unit to precharge the pair of local input / output lines by a first precharging unit, equalizing the pair of local input / output lines by an equalizing unit, and to precharge the local input / output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated.

A method and apparatus for reducing speckle due to MSL, without any loss of resolution, by averaging over different angles of the incident light at low input resolution, while collecting the backscattered light at a full resolution of a lens is described. The present invention allows discrimination against the speckle due to coherent MSL.

The method includes: receiving a first Non Return to Zero (NRZ) data signal and a synchronous clock signal, and performing Return to Zero (RZ) processing to generate a first complementary RZ data signal pair; receiving a second NRZ data signal and a synchronous clock signal, and performing RZ processing to generate a second complementary RZ data signal pair; and modulating the first complementary RZ data signal pair and the second complementary RZ data signal pair on light to generate an RZ-Differential Quadrature Phase Shift Keying (RZ-DQPSK) optical signal. Through the method and device, RZ processing are performed on the NRZ data signals to generate the complementary RZ data signal pairs, and the complementary RZ data signal pairs are modulated on the light, thereby reducing the cost and the insertion loss of the entire device, lowering the requirements for input optical power and reducing the complexity of loop circuit control.

A low input-current harmonic three-phase boost rectifier includes an input stage for receiving a three-phase input voltage in relation to a neutral node and an output stage adapted to couple to at least one load. The rectifier further includes one or more switching converter stages, each having a plurality of switches coupled to the neutral node, the plurality of switches operating with a fixed duty cycle, the fixed duty cycle being a substantially 50% duty cycle. The rectifier further includes one or more controllers adapted to vary the switching frequency of the plurality of switches based on at least one of a condition of the at least one load or the input voltage and includes one or more decoupling stages, each including one or more inductive elements adapted to inductively decouple the output stage from at least one of the one or more switching converter stages.

A constant-voltage power circuit incorporating an over-current protection circuit having a fold back current limiting capability operative through low input voltages, and being capable of arbitrarily setting current outputs. The constant-voltage power supply circuit is configured so that a voltage output with small amplitude from a differential amplifier circuit is subjected to amplitude expansion to be amplified to range fully from the ground potential approximately to the input voltage by means of an amplitude expansion circuit, which includes an inverter consisting of an NMOS transistor and a resistor, and that the voltage resulting from the amplitude expansion is subsequently input to the gate of a PMOS transistor configured to directly control an output transistor.

Two versions of an isolated single stage converter AC / DC Power Factor Corrected (PFC) converter topology have been invented. One is with a full bridge rectifier at its input and the other is a True Bridgeless version. The two versions of the topology feature new configurations and circuitry including a simplified damper circuit and a clamp capacitor flipping circuit and control methods that allow them to realize improved single stage isolated power factor converters which are suitable for high power operation, features Zero Voltage Switching to maximize conversion efficiency and to minimize Electro-Magnetic Interference generation, does not need an additional circuit to limit the inrush current, achieves reasonably low input current Total Harmonic Distortion (THD), and is easy to control. The second version provides a true bridgeless single stage isolated power factor converter with even higher efficiency and lower input current THD.

The invention relates to an automatic testing technology for molectron, in particular to an automatic testing method for multiple chips based on field programmable gate array (FPGA). According to the technical scheme provided by the invention, the field programmable gate array comprises the sample circuits that are connected to each other, a circuit of digital comparator, an encoder, and a pulse generating circuit. The technical scheme is characterized in that the input end of the circuit of digital comparator is connected with the output end of a multiplexer, the input end of the sample circuit is connected with a plurality of chips being tested; and the pulse generating circuit is connected with a plurality of chips being tested and a tested chip respectively; the output end of the encoder circuit is connected with the multiplexer. The invention uses the field programmable gate array (FPGA) to set up a simple automatic testing system, in which the automatic testing of a single or a plurality of chips can be implemented simultaneously on a testing board, The invention achieves automatic testing and has low input cost and rapid development, thus completely satisfying the requirement for the testing of small-lot products.

An auxiliary power supply or bias voltage supply employs a step up switch mode DC / DC power converter topology to supply regulated bias supply voltages, from very low input voltages (e.g., less than 2V). The supply will synchronize to dynamic loads making it particularly useful in circuits with periodic high peak current power demands, for example, gate drive circuits employed in regulated switched mode power converters. When unladed, the supply will efficiently adjust its cycle period to the minimum required to maintain the desired boosted output voltage. Additional transformer windings or a charge pump may be used to generate additional vias voltage sources.

The invention discloses a comprehensive error correction method of a short-period wind power prediction system. The method comprises wind power plant power output link error correction and numerical value weather forecast link error correction; the step of correcting an error of a wind power plant power output link comprises the steps of calculating the best modeling granularity of a power output model, accumulating after modeling by a plurality of fans instead of a single unit, rejecting an abnormal data point on a scatter diagram of the power output model with a times-variance method, and correcting the system error of the power output model by related factors; the step of correcting an error of a numerical value weather forecast link comprises the steps of obtaining a leading value weather forecast wind speed sequence by comparing actually measured wind speed with related coefficients of the numerical value weather forecast wind speeds in different time and space and correcting the system error, and correcting a cold front arrival time-delay error by a correlation analysis method. As to the problem of low input data quality of the existing short-period wind power prediction system, the comprehensive error correction method is generally applicable to various short-period wind power prediction methods, and can be conveniently applied to actual engineering, so that the modeling precision and the prediction precision of the short-period wind power prediction can be obviously improved.

A low input-current harmonic three-phase boost rectifier includes an input stage for receiving a three-phase input voltage in relation to a neutral node and an output stage adapted to couple to at least one load. The rectifier further includes one or more switching converter stages, each having a plurality of switches coupled to the neutral node, the plurality of switches operating with a fixed duty cycle, the fixed duty cycle being a substantially 50% duty cycle. The rectifier further includes one or more controllers adapted to vary the switching frequency of the plurality of switches based on at least one of a condition of the at least one load or the input voltage and includes one or more decoupling stages, each including one or more inductive elements adapted to inductively decouple the output stage from at least one of the one or more switching converter stages.

Disclosed are apparatus and methods for preparing wellbore viscous treatment gels from dry polymer and water. The apparatus includes an eductor which slurries dry polymer with water, at least two input tubes, wherein one input tube is connected with the eductor, and another to a water source. The apparatus also includes a mixing chimney connected to the input tubes. The mixing chimney includes a lower input section with inlets connected to the input tubes wherein a jet of metered dilution water is applied at high pressure to the incoming polymer-water slurry stream. This mixture is then accelerated in a circular, and preferably upward, motion where it is sheared against the wall of a central section of the chimney, without the use of an impeller. The chimney further includes an output section that comprising holes circumferentially located, through which the mixture passes from the central section and into a hydration tank. The mixture exiting the chimney is polymer-water gel which is essentially fully mixed and de-aerated, and at least partially hydrated.