6601 results about "Inverter" patented technology

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

A static random access memory (SRAM) device and a method for manufacturing the same are disclosed. In the SRAM device including a flip-flop circuit including two access transistors and a pair of inverters, connection lines for connecting the inputs and outputs of the inverters, and a word line, power supply lines and bit lines are formed of a metal interconnection. The resistance of interconnection can be reduced and the SRAM device manufacturing process can be performed along with CMOS standard logic manufacturing process.

The invention relates to a grid synchronizer for connecting an AC output of a power converter to the AC grid mains. In one aspect the invention provides a grid synchronizer comprising an inverter controller to control an AC output of the inverter, the controller including a receiver to receive grid data from a grid sensor location remote from said inverter. In another aspect we describe techniques for rapid removal of charge from a control terminal of a power switching device such as a MOSFET, IGBT or Thyristor using a particular driver circuit.

An integrated torsional mode damping method for a current source converter, including a rectifier, an inverter, and a DC link inductor coupled between the rectifier and the inverter, includes sensing a signal representative of torque on a shaft coupled to the inverter or rectifier; using the sensed signal for detecting a presence of a torsional vibration on the shaft; and damping the torsional vibration by modulating active power through the respective inverter or rectifier.

A motor driving apparatus has a loss-of-synchronism monitoring circuit that monitors the rotation of a rotary machine such as a brushless DC motor to detect a sign of transition to a state of loss of synchronism. When the sign is detected, an energization control circuit temporarily stops driving of the rotary machine to bring it into a free running state, and thereafter carries out control so as to resume driving of the rotary machine. Further, the motor driving apparatus has an inverter and a drive control circuit that controls switching operation of the inverter based on rotation of the rotary machine.

A method and apparatus for converting DC input power to AC output power. The apparatus comprises an input capacitor, a DC-AC inverter, a burst mode controller for causing energy to be stored in the input capacitor during at least one storage period and the energy to be drawn from the input capacitor during at least one burst period, wherein the AC output power is greater than the DC input power during the at least one burst period; a first feedback loop for determining a maximum power point (MPP) and operating the DC-AC inverter proximate the MPP; and a second feedback loop for determining a difference in a first power measurement and a second power measurement, producing an error signal indicative of the difference, and coupling the error signal to the first feedback loop to adjust at least one operating parameter of the DC-AC inverter to drive toward the MPP.

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and / or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and / or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and / or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feed back loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

A control system (20) for a power converter (22) designed to convert DC power from a source (30) such as a battery, flywheel or fuel cell into AC power. The control system includes an impedance current regulator (106) for providing an impedance current signal to a summing unit (110) where it may be combined with real and reactive current command signals provided from respective sources (62, 64). The resultant current signal provided by the summing unit is provided to a voltage correction unit (112) that uses the resultant current signal in developing a correction voltage signal provided to the power converter. The correction voltage signal contains information used by the power converter in adjusting the real and reactive currents in its output AC power based on the ability of the AC power network to accept changes in current. Multiple power converters having the control system of the present invention may be connected in parallel to a single AC load or multiple AC loads, without the need for a separate control system interconnecting the power converters. The control system may be advantageously incorporated into a distributed generation network and in uninterruptible power systems, whether or not such systems are included in a distributed generation network.

A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.

A fault inrush transient current restraining type virtual synchronous inverter and thereof is disclosed. The invention solves the problem that a virtual synchronous inverter will be burned due to inrush transient current in an extreme situation of a symmetrical fault occurring on the grid side by setting an information collection module for inverter output voltages and currents, a virtual synchronous inverting control module, a fault detection and synthesize module, a hysteresis comparison control module and a post fault clearing switch back grid-tie control module.

Each of three-phase arm of an inverter has first and second switching elements connected in series together at a connection point to the corresponding phase coil of the three-phase motor. Control device turns on the first switching element of the i-th (i is a natural number smaller than four) for a predetermined time period, and determines that the second switching element of the i-th arm has a short fault, when an overcurrent exceeding a predetermined threshold is detected within the predetermined time period. The predetermined time period is shorter than a time period from a time point of turning on the first switching element of the i-th arm to a time point of attaining the predetermined threshold by a current flowing through a path extending from a power supply line through the second switching element of the remaining arm other than the i-th arm to a ground line.

The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.

The subject matter of the invention is an inverter (3), more specifically for use in a photovoltaic plant (1) with a direct voltage input (connection terminals 4; 5) for connection to a generator (2) and an alternating voltage output (connection terminals 7; 8) for feeding into an energy supply network (6) as well as with a DC-AC converter (12) with semiconductor switch elements (15) and an intermediate circuit (11), at least one short-circuit switch element (18) being connected in parallel to the generator (2), so that the voltage will not exceed a maximum voltage value neither at the connection terminals (4; 5) of the generator (2) nor between the connection terminals (9; 10) of the inverter. This is achieved in that the inverter (3) comprises, in the intermediate circuit (12), a buffer capacitor (14) that is connected to the generator (2) through a protection diode (17) so that said buffer capacitor (14) will not be discharged upon actuation of the short-circuit switch element (18), the generator (2) working according to a clock rate in the short-circuit mode of operation.

The invention relates to a pulse-width modulation (PWM) output method for solving the problem of nonuniform heating of a bridge arm switch of a single-phase full-bridge inverter circuit. The PWM output method is characterized in that two bridge arms use the modulation wave period T as an interval for alternately outputting PWM waves and square wave voltage. The problem of nonuniform heating caused by great work frequency differences of two bridge arm switches is solved, the temperature of an overheat switch is obviously reduced, insulated gate bipolar translator (IGBT) power switch device faults caused by overheat is effectively overcome, the reliability of a switch device is favorably improved, and the service life is prolonged.

The invention relates to a high frequency heating apparatus that drives a magnetron such as a microwave, and provides a frequency modulation method of preventing harmonic current occurring due to a high frequency switching operation. When a driving signal is transmitted in order to drive a first semiconductor switching element (3) and a second semiconductor switching element (4), an inverter operating frequency in the every phase of a commercial power supply is provided as a frequency difference (inclination) of the phase range from 0° to 90° using a triangular wave-forming circuit in an oscillation circuit (16). A modulation waveform for a frequency modulation control is formed, configuring an upper limit clamp, a lower limit clamp, a lower limit value corresponding to the lowest frequency in a frequency modulation-forming circuit (15) on the basis of a commercial power rectifying voltage-dividing waveform after rectification. By combining these optimally, it is possible to prevent the harmonic current from occurring while forming the frequency modulation waveform handling several non-uniformities such as constants of major inverter circuit components or a power supply (Vcc) of a driving control IC unit (14).

When a rectangular wave voltage control mode is selected, a control apparatus estimates the output torque of an alternating-current motor based on the outputs of a current sensor and a rotation angle sensor, and executes torque feedback control by adjusting the phase of rectangular wave voltage based on the difference between the torque estimated value and a torque command value. The control apparatus executes a switching interruption that outputs a control command to a switching element of an inverter every 60 degrees of electrical angle, and executes an angle interruption that samples the phase currents of the alternating-current motor based on the output of the current sensor and converts those phase currents into a d-axis current and a q-axis current every predetermined electrical angle that is set beforehand. The control apparatus for the alternating-current motor then sets the predetermined electrical angle such that the number of angle interruptions between switching interruptions varies according to the rotation speed of the alternating-current motor.

An inductance parameter identification method of a synchronous motor and an implementation system thereof are provided. The method comprises: applying a three-phase balance high frequency voltage or current signal to the synchronous motor; sampling a feedback high frequency current or voltage of the synchronous motor; extracting positive sequence and negative sequence component amplitude of the feedback high frequency current or voltage which has the same frequency of the injecting voltage or current; and calculating to get d-axis inductance Ld and q-axis inductance Lq of the synchronous motor. Identification of the d-axis inductance and q-axis inductance of the synchronous motor can be implemented more accurately on a general inverter on the basis of non-increase of hardware cost. The method and system have the following advantages of implementing easily, not high demand for the motor feedback current sampling accuracy, and controlling easily for the frequency and amplitude of the high frequency voltage signal injected into the motor, and identifying to get the d-axis inductance and q-axis inductance of the motor directly no matter the motor shaft is in a free state, or in a hold tight stage, which do not affect accuracy of identification.

A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.

The invention discloses a testing system and a method for electric part of power system for weak hybrid electric vehicle, and the system comprises a BSG motor module provided with a BSG motor and a BSG motor controller; a dynamometer module provided with a dynamometer, a measuring and control instrument and a torque and speed sensor, and a transducer or an inverter; a power module provided with a power storage battery, a battery management system, a program control power supply and a program control power supply controller; an auxiliary electric system load simulation module provided with a DC / DC convertor and an auxiliary electric system load; an upper computer module. The method adopts the half object simulation principle, the dynamometer simulates the engine for doing test to the BSG motor module and does the service life test for the electric part of weak hybrid power system at different working conditions that the BSG motor starts the engine, the engine drives the BSG motor for generating, regenerative braking, idle parking while the battery drives the load, the system and method can reduce the test cost, shorten the test period for vehicle performance and raise the developing speed for product.

The subject matter of the invention is an inverter with a housing (1) having a cooling unit (2) for cooling the electronic and / or electric components (4, 5, 5a) of the inverter, the housing (1) of the inverter comprising at least two chambers, said two chambers (7, 8) being separated by a wall (6) for receiving the lossy components (4, 5, 5a), said components (5), if they comprise cooling bodies (4), being located on the one side of the wall in the one chamber (7) with the cooling bodies (4) being located on the other side of the wall (6) in the other chamber (5) and, if the very electric or electronic component to be cooled (5a) has a high protection grade, said component (5a) being located in the other chamber (8), preferably on the wall side of the wall (6) of the other chamber (8), said other chamber (8) comprising the cooling unit (2).

The invention relates to a multi-inverter module paralleling frequency conversion device for a transmission system and a control policy. The device comprises a rectifier, inverters, a braking device, a cooling system, a protection device, an interface and the like, and is characterized in that an inverter paralleling structure realizes a relatively high power factor; through the parallel connection of multiple rectifying modules and the parallel connection of multiple inversion units, the output capacity of the inverters is increased, and the input / output harmonic waves are reduced; a control box drives a motor to operate by controlling the work of a frequency converter; and a fuse group and control power supply perform fault protection on the system and provide power to each part. In the control policy, a motor driving mode that master and slave modules perform hierarchical control is adopted; as the master control module synchronizes the slave control module, the problem of difficult same-frequency and same-phase output of multiple inverters in the case of motor load is solved; by monitoring the current of each inversion module (multiple inversion modules) and dynamically adjusting the output of each inversion module, the key technology of realizing homogeneous flow of the outputs of multiple paralleling inversion modules is broken through, and an inverter paralleling frequency conversion and speed regulation control method with relatively high static and dynamic performance is realized; and high power of the frequency conversion device with multiple paralleling inversion modules for the transmission system is realized.

An inverter (22) is provided between a power source (20) and a suction / discharge valve driving motor (14) that controls cycle time of suction and discharge of a refrigerator unit (10). An output frequency of the inverter (22) is controlled in accordance with output of a sensor (24) that detects temperature of a thermal load portion (11) of the refrigerator unit (10). This enables temperature adjustment of individual refrigerators with a highly reliable method without using an electric heater.

The method and circuit for controlling a sensorless single-phase BLDCM having a stator with a winding are proposed. The provided controlling circuit includes a power supply circuit, an inverter coupled to the winding and the power supply circuit, a BEMF detecting circuit coupled to the winding and the inverter and measuring a BEMF of the winding, and a controller coupled to the power supply circuit, the inverter and the BEMF detecting circuit and analyzing a status of the BEMF to control the BLDCM accordingly. The provided method is based on the motor winding time-sharing theory, and the controller controls the inverter to make the winding used as a driving element with loading current when the absolute value of the BEMF is relatively large and as a sensing element when the absolute value of the BEMF is relatively small.

The invention discloses a resolution method and a resolver for signals of a rotating transformer. The method comprises the steps of: acquiring a rotating angle signal of a motor and establishing a sine table, sampling a current low-frequency sinusoidal signal and a current low-frequency cosine signal, dividing the angle position of a rotor into four quadrants, and determining the quadrant which the position of the rotor belongs to; and performing the lookup of the sine table according to the low-frequency sinusoidal signal and the position of the rotor, and judging the rotation direction of the rotor. A sinusoidal excitation signal generator is connected with the rotating transformer and differential signal converters, and a sinusoidal differential signal feedback by the rotating transformer passes through the differential signal converter, then is input into a precision absolute value adder along with a reference signal, passes through a low-pass filter and then is input into a digital signal processor; and a cosinoidal differential signal feedback by the rotating transformer passes through another differential signal converter, then is input into the precision absolute value adder along with the sinusoidal excitation signal which passes through a phase inverter, passes through the low-pass filter and then is input into the digital signal processor. The resolution method and the resolver greatly reduce the cost, and can perform accurate sampling and conversion on input signals.

A programmable matched filter bank comprises a sliding integrator and compensation calculation circuits. The integrator receives a chip stream of samples derived from a received spread-spectrum signal and integrates a number of the most recent samples, to form a common integration value. Each of the compensation calculation circuits receives the same most recent samples and receives a respective one of the possible reference spreading code sequences. In operation, each compensation calculation circuit derives a compensation value, and an associated circuit modifies the common integration value by the respective compensation value. The result is a value of correlation between the predetermined number of most recent samples, for each respective reference code sequence. The inventive approach reduces the number of bit adders and inverters in the implementation of a matched-filter, a programmable matched filter and a programmable matched filter bank for spread spectrum receivers.

The invention relates to a master-slave control strategy microgrid-based main power supply double-mode running control method which belongs to the technical field of distributed power generation. The method comprises the following steps of: when switching from an independent running mode to a grid-connected running mode, switching a control manner from voltage and current double-ring control intocurrent closed ring control and memorizing a voltage ring output result before switching as switched current ring reference input; memorizing a current ring output result before switch as an initial value of a switched current ring output result; when switching from the grid-connected running mode into the independent running mode, switching the control manner from current closed ring control into voltage and current double-ring control and memorizing a current ring reference input command before switch as an initial value of a switched voltage ring output result; and memorizing the current ring output result before switch as the initial value of the switched current ring output result. The control method provided by the invention can ensure that all output quantities of a two-way inverter can not be mutated, and the microgrid system transient process is smoother.

An inverter control apparatus and a control method thereof are provided. The inverter control apparatus and a control method thereof stably operate a three-phase motor using a capacitor having a small capacitance for a DC link. The inverter control apparatus includes a current sensor to sense an output current of the inverter, a voltage sensor to sense a DC-link voltage of the inverter, and a controller to generate an average of a periodically varying rotor based q-axis current boundary value based on the output current and the DC-link voltage to generate a current reference on the basis of the average of the rotor based q-axis current boundary value, and to drive a three-phase motor based on the current reference. Stabilized variable speed control of a motor by using a small-capacitance capacitor for a DC link of an inverter is performed and reliability of an inverter circuit improved.

A control apparatus for a multiphase AC electric motor having an inverter includes a current control including an abnormal-state current controller; an abnormal-state detector that detects an abnormal state of any of a wire of an electric motor, a wire of an inverter, and a wire connecting the electric motor to the inverter as an abnormal phase; and an abnormal phase disconnect. The abnormal phase disconnect disconnects one or more of phases detected to be in an abnormal-state and the abnormal-state current controller generates an abnormal state voltage command in accordance with detection of an abnormal state, and uses phases other than the disconnected phases of the inverter to control individual currents of the phases, with the abnormal-state voltage command used as a multiphase voltage command.

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.