6511 results about "Inverter" patented technology

A static random access memory (SRAM) device and a method for manufacturing the same are disclosed. In the SRAM device including a flip-flop circuit including two access transistors and a pair of inverters, connection lines for connecting the inputs and outputs of the inverters, and a word line, power supply lines and bit lines are formed of a metal interconnection. The resistance of interconnection can be reduced and the SRAM device manufacturing process can be performed along with CMOS standard logic manufacturing process.

A method and apparatus for converting DC input power to AC output power. The apparatus comprises an input capacitor, a DC-AC inverter, a burst mode controller for causing energy to be stored in the input capacitor during at least one storage period and the energy to be drawn from the input capacitor during at least one burst period, wherein the AC output power is greater than the DC input power during the at least one burst period; a first feedback loop for determining a maximum power point (MPP) and operating the DC-AC inverter proximate the MPP; and a second feedback loop for determining a difference in a first power measurement and a second power measurement, producing an error signal indicative of the difference, and coupling the error signal to the first feedback loop to adjust at least one operating parameter of the DC-AC inverter to drive toward the MPP.

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feed back loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

Each of three-phase arm of an inverter has first and second switching elements connected in series together at a connection point to the corresponding phase coil of the three-phase motor. Control device turns on the first switching element of the i-th (i is a natural number smaller than four) for a predetermined time period, and determines that the second switching element of the i-th arm has a short fault, when an overcurrent exceeding a predetermined threshold is detected within the predetermined time period. The predetermined time period is shorter than a time period from a time point of turning on the first switching element of the i-th arm to a time point of attaining the predetermined threshold by a current flowing through a path extending from a power supply line through the second switching element of the remaining arm other than the i-th arm to a ground line.

The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.

The invention relates to a pulse-width modulation (PWM) output method for solving the problem of nonuniform heating of a bridge arm switch of a single-phase full-bridge inverter circuit. The PWM output method is characterized in that two bridge arms use the modulation wave period T as an interval for alternately outputting PWM waves and square wave voltage. The problem of nonuniform heating caused by great work frequency differences of two bridge arm switches is solved, the temperature of an overheat switch is obviously reduced, insulated gate bipolar translator (IGBT) power switch device faults caused by overheat is effectively overcome, the reliability of a switch device is favorably improved, and the service life is prolonged.

When a rectangular wave voltage control mode is selected, a control apparatus estimates the output torque of an alternating-current motor based on the outputs of a current sensor and a rotation angle sensor, and executes torque feedback control by adjusting the phase of rectangular wave voltage based on the difference between the torque estimated value and a torque command value. The control apparatus executes a switching interruption that outputs a control command to a switching element of an inverter every 60 degrees of electrical angle, and executes an angle interruption that samples the phase currents of the alternating-current motor based on the output of the current sensor and converts those phase currents into a d-axis current and a q-axis current every predetermined electrical angle that is set beforehand. The control apparatus for the alternating-current motor then sets the predetermined electrical angle such that the number of angle interruptions between switching interruptions varies according to the rotation speed of the alternating-current motor.

An inductance parameter identification method of a synchronous motor and an implementation system thereof are provided. The method comprises: applying a three-phase balance high frequency voltage or current signal to the synchronous motor; sampling a feedback high frequency current or voltage of the synchronous motor; extracting positive sequence and negative sequence component amplitude of the feedback high frequency current or voltage which has the same frequency of the injecting voltage or current; and calculating to get d-axis inductance Ld and q-axis inductance Lq of the synchronous motor. Identification of the d-axis inductance and q-axis inductance of the synchronous motor can be implemented more accurately on a general inverter on the basis of non-increase of hardware cost. The method and system have the following advantages of implementing easily, not high demand for the motor feedback current sampling accuracy, and controlling easily for the frequency and amplitude of the high frequency voltage signal injected into the motor, and identifying to get the d-axis inductance and q-axis inductance of the motor directly no matter the motor shaft is in a free state, or in a hold tight stage, which do not affect accuracy of identification.

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a “standard” triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10–50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

The invention discloses a single event radiation effect resistant reinforced latch circuit. The single event radiation effect resistant reinforced latch circuit comprises a first transmission gate unit, a second transmission gate unit, a Schmitt inverter, a conventional input separation inverter, a first input separation clock-controlled inverter, a second input separation clock-controlled inverter, a delay circuit and a MullerC unit circuit. When the single event radiation effect resistant reinforced latch circuit operates under a transparent mode, a hysteresis effect of the Schmitt inverter and a delay difference of a latch interior unit are effectively used and SET pulses from a combinational logic unit are shielded through the MullerC unit; when the single event radiation effect resistant reinforced latch circuit operates under a latch mode, any interior node generating SEU due to the irradiation effect can be recovered through states of other nodes through a DIC unit structure having a self-recovery capability and correct output of the latch is guaranteed; accordingly the single event radiation effect resistant reinforced latch circuit has the advantages of effectively eliminating the radiation effect influences and being applicable to a clock gating circuit and small in power consumption and area costs.