Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

9280 results about "Low power dissipation" patented technology

LED array primary display light sources employing dynamically switchable bypass circuitry

The invention comprises use of Dynamically Switchable Bypass (DSB) elements in association with one or more Light Emitting Diodes (LEDs) in arrays for illumination circuits to provide rugged, reliable lighting. The DSBs are selected from Transient Voltage Suppressors, including Silicon, Metal Oxide Varistors, and Multi Layer Varistors as well as Zener Diodes. The DSBs are not used as circuit protecting devices, but rather as alternative paths for electric current to bypass failed LEDs. Bi-directional TVSs are used as alternative electric paths for circuits using Alternating Current (AC) and parallel LED arrays that light on both phases of AC. Zener Diodes are used in parallel to, but in the opposite polarity orientation to, one or more LEDs in DC or rectified AC circuits. The inventive paired DSB/LED elements overcomes the black-out problems of prior series LED illumination systems, making possible the use of robust LEDs in illumination systems where reliability, long life, low power consumption, low heat output, resistance to shock, vibration, and humidity, and self-diagnosis are important. The DSB elements have breakdown voltages slightly higher than the LED(s) they support, so that when an LED fails, the conduction through the DSB begins. Because the conduction voltage of the DSB so nearly matches the conduction voltage of the LED(s), the remainder of the circuit continues to function as normal. The system is self-diagnostic in that any LED failure presents itself as a dark LED rather than as a whole string of dark LEDs. DSBs may be used with incandescent bulbs.
Owner:IDD AEROSPACE

Method of placing and routing for power optimization and timing closure

A method, algorithm, software, architecture and / or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and / or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.
Owner:GOLDEN GATE TECH

Novolatile semiconductor memory device and manufacturing process of the same

There is provided a nonvolatile semiconductor memory device which can shorten data writing and erasing time, significantly improve the endurance characteristic and be activated with low power consumption. The nonvolatile semiconductor memory device comprises an insulating layer 3b with electric insulation, wherein, a charge retention layer 3 formed adjacent to a tunnel insulating film 2 contains nano-particles 3a comprised of a compound which is constituted from at least one single-element substance or chemical compound having a particle diameter of at most 5 nm functions as a floating gate, and which are independently dispersed with a density of from 10+12 to 10+14 particles per square centimeter.
Owner:ASAHI GLASS CO LTD +1

Apparatus and method for reducing power consumption by adjusting backlight and adapting visual signal

Backlight intensity is adjusted in a terminal. An adaptation apparatus transmits a visual signal after optimizing brightness or contrast of the visual signal based on the backlight intensity information which is related to the adjusted backlight intensity, so that the user can enjoy digital item with reduced power consumption of the terminal.
Owner:ELECTRONICS & TELECOMM RES INST
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products