A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.