113 results about "Planar capacitor" patented technology

A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line, wherein back channel effect is suppressed adding additional ions in the bottom side of third terminal or applying negative voltage in the well or substrate. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation. In this manner, no holding current is required during standby, and operating current is dramatically reduced with no negative generator. Write has a sequence to clear the state of cell before writing to store data regardless of previous state. Refresh cycle is periodically asserted to sustain data. The present invention can be applied for destructive read, or for nondestructive read adding pull-down device to bit line. The height of cell is almost same as control circuit on the bulk or SOI wafer.

A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.

A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.

The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

A foot controller for electrically controlling a device by a user may include at least one sensor pad module having a first plate of dielectric material. The first plate of dielectric material may support at least two electrodes forming a planar capacitor. The controller may further include a second plate of dielectric material separated from the first plate by a layer of compressible dielectric material. The first plate is adapted to be displaced with respect to the second plate, so as to vary the geometry of an equivalent capacitor which includes the at least two electrodes, the compressible dielectric material and the second plate of dielectric material, thereby varying the value of the capacitance of the equivalent capacitor. The foot controller may further include a control module adapted to generate an electrical control signal which depends on the value of the capacitance.

A kind of flat capacitance-type sensor includes a flat capacitor, a flat capacitance compensator which eliminate interfere signal and a sensor detecting circuit. The invention adopts double-flat capacitance, thereinto one is used as measuring capacitance; another is as compensating capacitance, it is insensitive with rain water of outer surface by changing mounting position and shape of compensating capacitance, and sensitive with temperature shift and electromagnetic interfere. When there is temperature shift or electromagnetic interfere, the value of measuring capacitance and compensating capacitance change at the same time and extent are similar, when rain water is changed, value of measuring capacitance changes, but value of compensating capacitance does not change. Using characters above can difference compensate measuring of sensor, disadvantageous affects of temperature shift and electromagnetic interfere can be decreased, error action of rain shaving can be avoided.

A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM / PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.

The invention belongs to the technical field of energy storage devices, and particularly relates to a transparent flexible supercapacitor fabric and a preparation method of the transparent flexible supercapacitor fabric. According to the method, oriented carbon nano tube fiber is woven into a carbon nano tube fiber fabric, a carbon nano tube / polyaniline composite fabric is obtained by depositing polyaniline on the carbon nano tube fiber fabric through an electrochemical deposition method, the surface of the composite fabric is coated with one layer of polyvinyl alcohol / phosphoric acid (PVA / H3PO4) gel electrolyte, and finally the product is assembled with the other electrode with the same structure and material so that the supercapacitor fabric can be obtained. Compared with a traditional planar capacitor, the supercapacitor fabric has the advantages of being light in weight, capable of being woven and the like; compared with other fabric capacitors, the supercapacitor fabric has the advantages of being transparent and the like; compared with a fiber supercapacitor, the supercapacitor fabric is higher in large-scale weaving capacity, and thus the supercapacitor fabric has very good application prospects.

The present invention relates generally to polymer composites having dispersed therein both useful spinel crystal fillers and ferroelectric (and / or paraelectric) fillers wherein the composite is both light activatable and can be used as a planar capacitor material. The light activation is typically employed via a laser beam (or other light emitting device) where the material has a pattern formed thereon. Electrodes are typically formed on the material's surface after patterning is complete via electroless metal plating. These composite polymers can be used as planar capacitors embedded in printed wiring boards or in integrated circuit packages.

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

A power core comprising: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded singulated capacitor; and wherein said embedded singulated capacitor is connected in parallel to said planar capacitor laminate.

An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.