99results about How to "Reduce step height" patented technology

A radially segmented apodized diffractive multifocal IOL for ocular implant is provided. The ocular implant can comprise a radially segmented apodized diffractive multifocal intraocular lens optic and a number of haptics. The radially segmented apodized diffractive multifocal IOL may pass optical energy in both photopic and mesopic conditions. The radially segmented apodized diffractive multifocal IOL includes a number of radially segmented apodization zones, each radially segmented apodization zones having a unique focal length. The haptics mechanically couple to the apodized diffractive multifocal IOL optic in order to position and secure the apodized diffractive multifocal IOL within the eye. The radially segmented apodized diffractive multifocal IOL may include both a diffractive region and a refractive region.

An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

An isolator is partially but substantially recessed in an acoustic floor and a leveling mechanism at least partially recessed in the acoustic floor is connected to the acoustic isolator to adjust the height of the acoustic floor when the floor is in place.

A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source / drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

A fold-and-dive structure for a vehicle seat is provided, which includes a connection member connecting a cushion frame built in a seat cushion and a back frame built in a seat back to each other, a rotating link connecting a front end portion of the cushion frame and a support frame to each other, and a recliner provided on the support frame to which a lower end portion of the back frame is rotatably connected, wherein a guide frame is provided on a front side portion of the connection member, and the cushion frame is slidably coupled to the guide frame to make the seat cushion slide forward.

An organic light emitting display which is constructed with a TFT substrate having an insulating substrate and a TFT that has at least a source electrode and a drain electrode, a lower electrode formed on the TFT substrate and connected to one of source / drain electrodes, an insulating layer having an opening that exposes a portion of the lower electrode, an organic thin film layer formed on the exposed portion of the lower electrode and the insulating layer, and an upper electrode formed on the organic thin film layer, wherein the insulating layer has a taper angle less than 40° at an edge of the opening, and a step less than or equal to 3,000 Å is formed between the lower electrode and the organic thin film layer. The organic light emitting display can prevent device failure.

The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source / drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source / drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.

An exercise apparatus includes a housing, a pair of pivoting foot treadles and a pair of reciprocating bellows that support the foot treadles. A sealed air system including a conduit interconnects the bellows and is operable for reciprocating transfer of air from bellow to bellow. Each of the foot treadles is pivotably movable between upper and lower positions, and has a resting position between the upper and lower positions. The resting position of the foot treadles defines a resting position of the bellows while the upper and lower positions of the foot treadles respectively define elongated and compressed positions of the bellows. In use, the elongated and compressed positions of the bellows are each no more than 5 degrees off the center resting position thereby reducing stress on the bellows.

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

An active organic electroluminescence panel display and a fabricating method thereof are disclosed. A thin film transistor array comprising a plurality of thin film transistors, a plurality of datalines and a plurality of scanlines are formed on a substrate. A passivation layer is formed on the substrate, covering the thin film transistor array. A contact opening is formed in the passivation layer for exposing a prescribed area of the array. An anode layer is formed on the passivation layer and fills into the contact opening. A blank layer is formed on the anode, covering the contact opening. A shadow mask is disposed on the blank layer. Then, a sputtering process is performed to form an organic luminescent layer. The shadow mask is then removed, and a cathode layer is formed on the organic luminescent layer for forming an active organic electroluminescence panel display.

A method of manufacturing a transistor, typically a MESFET, includes providing a substrate including single crystal diamond material having a growth surface on which further layers of diamond material can be deposited. The substrate is preferably formed by a CVD process and has high purity. The growth surface has a root-mean-square roughness of 3 nm or less, or is free of steps or protrusions larger than 3 nm. Further diamond layers are deposited on the growth surface to define the active regions of the transistor. An optional n+ shielding layer can be formed in or on the substrate, following which an additional layer of high purity diamond is deposited. A layer of intrinsic diamond may be formed directly on the upper surface of the high purity layer, followed by a boron doped (“delta doped”) layer. A trench is formed in the delta doped layer to define a gate region.

According to a polarized glasses type stereoscopic image display device and a fabrication method thereof in accordance with the present invention, a light blocking pattern may be formed on a rear surface of the color filter substrate to enhance vertical viewing angle and aperture ratio. Moreover a light blocking pattern may be formed of a metal having a large hardness instead of resin BM and a step height from the rear surface ITO may be removed to prevent a scratch due to an abrasive belt.

A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

A radially segmented apodized diffractive multifocal IOL for ocular implant is provided. The ocular implant can comprise a radially segmented apodized diffractive multifocal intraocular lens optic and a number of haptics. The radially segmented apodized diffractive multifocal IOL may pass optical energy in both photopic and mesopic conditions. The radially segmented apodized diffractive multifocal IOL includes a number of radially segmented apodization zones, each radially segmented apodization zones having a unique focal length. The haptics mechanically couple to the apodized diffractive multifocal IOL optic in order to position and secure the apodized diffractive multifocal IOL within the eye. The radially segmented apodized diffractive multifocal IOL may include both a diffractive region and a refractive region.

An electro-optical device for a liquid-crystal apparatus includes TFTs provided above a substrate, pixel electrodes that are provided above the TFTs and that are connected to corresponding relay electrodes via contact holes, a protection insulating film that is provided on the pixel electrodes from the gaps between the pixel electrodes to the edge portions thereof so as to cover end surfaces of the edge portions of the pixel electrodes, and an alignment layer that is provided on a surface including the protection insulating film and that is rubbed. Material residues of the alignment layer are reduced or prevented from being generated or trapped in the vicinities of the edges of the pixel electrodes and in the vicinities of the contact holes. Consequently, brightness irregularities or display irregularities are reduced.

An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

An exercise apparatus includes a housing, a pair of pivoting foot treadles and a pair of reciprocating bellows that support the foot treadles. A sealed air system including a conduit interconnects the bellows and is operable for reciprocating transfer of air from bellow to bellow. Each of the foot treadles is pivotably movable between upper and lower positions, and has a resting position between the upper and lower positions. The resting position of the foot treadles defines a resting position of the bellows while the upper and lower positions of the foot treadles respectively define elongated and compressed positions of the bellows. In use, the elongated and compressed positions of the bellows are each no more than 5 degrees off the center resting position thereby reducing stress on the bellows.

To ensure sealing ability of a resealable can container formed of a welded can body between a curled portion of container mouth and a resin sealing liner, without degrading productivity and easiness to open the closure.The can body 2 is prepared by rolling a steel sheet and welding overlapped longitudinal edges of the steel sheet. In order to achieve the above-mentioned objective, a level difference of a welded portion 2a on the surface of a curled portion 21a is reduced smaller than that on the trunk portion 22, specifically, kept within the range of 15 to 100 μm, and a durometer hardness of the resin sealing liner is kept within the range of HDA 30 to 70 according to ISO 868 (or JIS-K7215).

A method of reducing substrate step height. The method includes providing a substrate having a low-voltage device area and high-voltage device area divided by an isolation structure, forming an oxidation mask at least approximately 500 Å thick over the low-voltage device area and parts of the isolation structure, forming a first oxide layer on the exposed high-voltage device area and isolation structure using the oxidation mask as a mask, removing the oxidation mask, and forming a second oxide layer, thinner than the first oxide layer, on the low-voltage device layer.