4697results about How to "Reduce yield" patented technology

A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and / or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate / data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate / data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate / data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle / stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle / stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.

Backthinning in an area selective manner is applied to CMOS imaging sensors 12 for use in electron bombarded active pixel array devices. A further arrangement results in an array of collimators 51 aligned with pixels 42 or groups of pixels of an active pixel array providing improved image contrast of such image sensor. Provision of a thin P-doped layer 52 on the illuminated rear surface provides both a diffusion barrier resulting in improved resolution and a functional shield for reference pixels. A gradient in concentration of P-doped layer 52 optimizes electron collection at the pixel array.

In commercial products to which a non-contact type or contact type ID label or ID tag is attached and ID cards, there is fear that, due to a difference between coefficients of thermal expansion between an antenna for communication and a resin provided around the antenna, stress is applied to the resin with the larger coefficient of thermal expansion to break the resin. This contributes to decrease in manufacturing yield, lifetime, and reliability of an ID label or the like. In an article such as an ID label, an ID tag, and an ID card according to the present invention, a filler is included in a filling layer provided around an antenna forming an ID label, an ID tag, and an ID card so that the difference in coefficient of thermal expansion between the antenna and the filling layer can be reduced. This makes it possible to ease generation of stress due to the difference in coefficient of thermal expansion and prevent peeling and cracks of the filling layer.

Embodiments in accordance with the thin film write head of the present invention have a lower pole structure, an upper pole structure, and a multilayer write gap extending from an air bearing surface between the upper and lower pole structures. In preferred embodiments, the write gap comprises at least two of: (a) a first layer covering a lower pole tip portion of the lower pole structure, (b) a second layer covering turns of a semiconductor winding, or (c) a third layer covering a winding insulation stack. In more preferred embodiments, the write gap is formed of the first, the second, and the third write gap layers. An advantage of a write head with a multilayer write gap is that it allows better control of write gap thickness. As such, loss of write gap thickness can be compensated for by deposition of the second write gap layers, or by deposition of the third write gap layer. Some embodiments have one or more additional advantages in providing increased corrosion prevention, improving the integrity of conductor insulation, and / or improving the top pole magnetic material characteristics.

A circularly polarizing plate comprises a linearly polarizing membrane and a quarter wave plate. The quarter wave plate comprises an optically anisotropic layer A and an optically anisotropic layer B. The quarter wave plate has such an optical characteristic that a retardation value essentially is a quarter of a wavelength when the retardation value is measured at the wavelength of 450 nm, 550 nm and 650 nm. One of the optically anisotropic layers A and B is a layer made from liquid crystal molecules, and the other is a polymer film or a layer made from liquid crystal molecules.

This invention provides a process for hydrotreating hydrocarbon resins, which process comprises contacting a feedstock comprising a hydrocarbon resin or rosin, under suitable hydrotreating conditions, with a bulk multimetallic catalyst comprised of at least one Group VIII non-noble metal and at least two Group VIB metals and wherein the ratio of Group VIB metal to Group VIII non-noble metal is from about 10:1 to about 1:10. The process accord invention can achieve increased hydrocarbon resin productivity through increase in throughput volumes and effective catalyst lifetimes. The process of the invention is desirably practiced with a bulk catalyst consisting of only the combination of the metal species with the active metal components. The absence of carrier substrates largely removes the possibility of halogen accumulation on substrate surfaces that, in turn, can acidify metal catalysts such that additional, progressive cracking of the hydrocarbon resin molecules occurs.

The invention provides compositions comprising, 16alpha-bromo-3beta-hydroxy-5alpha-androstan-17-one hemihydrate and one or more excipients, typically wherein the composition comprises less than about 3% water. The compositions are useful to make improved pharmaceutical formulations. The invention also provides methods of intermittent dosing of steroid compounds such as analogs of 16alpha-bromo-3beta-hydroxy-5alpha-androstan-17-one and compositions useful in such dosing regimens. The invention further provides compositions and methods to inhibit pathogen (viral) replication, ameliorate symptoms associated with immune dysregulation and to modulate immune responses in a subject using certain steroids and steroid analogs. The invention also provides methods to make and use these immunomodulatory compositions and formulations.