14998 results about "Resist" patented technology

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

A method of depositing a silicon oxide film on a resist pattern or etched lines formed on a substrate by plasma enhanced atomic layer deposition (PEALD) includes: providing a substrate on which a resist pattern or etched lines are formed in a PEALD reactor; controlling a temperature of a susceptor on which the substrate is placed at less than 50° C. as a deposition temperature; introducing a silicon-containing precursor and an oxygen-supplying reactant to the PEALD reactor and applying RF power therein in a cycle, while the deposition temperature is controlled substantially or nearly at a constant temperature of less than 50° C., thereby depositing a silicon oxide atomic layer on the resist pattern or etched lines; and repeating the cycle multiple times substantially or nearly at the constant temperature to deposit a silicon oxide atomic film on the resist pattern or etched lines.

A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2 / N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr / O2 / Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr / O2 / Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

Methods for etching a metal layer using an imprinted resist material are provided. In one embodiment, a method for processing a photolithographic reticle includes providing a reticle having a metal photomask layer formed on an optically transparent substrate and an imprinted resist material deposited on the metal photomask layer, etching recessed regions of the imprinted resist material to expose portions of the metal photomask layer in a first etching step, and etching the exposed portions of the metal photomask layer through the imprinted resist material in a second etching step, wherein at least one of the first or second etching steps utilizes a plasma formed from a processing gas comprising oxygen, halogen and chlorine containing gases. In one embodiment, the process gas is utilized in both the first and second etching steps. In another embodiment, the first and second etching steps are performed in the same processing chamber.

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

In a coating and developing apparatus that forms a resist film on substrates such as semiconductor wafers, and develops substrates exposed by an aligner, times after the aligner unloads substrates until heating units (PEB) start heating the substrates are kept uniform. Exposed wafers are prevented from being left stagnant in an interface portion disposed between a region in which resist is coated and developed and the aligner. In the region in which resist is coated and developed, a first transferring means that successively executes transportation cycles to transfer substrates from upstream side modules to downstream side modules in a flow of processes of substrates. N heating units (PEB) are disposed (n is for example 5). Exposed wafers loaded into the heating units (PEB) are unloaded by the first transferring means after (n−1) cycles including the transferring cycle of the first transferring means have elapsed.

Cleaning solutions for photoresist are disclosed which are useful for cleaning a semiconductor substrate in the last step of development when photoresist patterns are formed. Also, methods for forming photoresist patterns using the same are disclosed. The disclosed cleaning solution comprises H2O as a solution, a surfactant which is phosphate-alcoholamine salt represented by Formula 1, and an alcohol compound. The disclosed cleaning solution has lower surface tension than that of distilled water which has been used for conventional cleaning solutions, thereby improving resistance to photoresist pattern collapse and stabilizing the photoresist pattern formation.wherein R, x, y, z, a and b are as defined in the specification.

The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate electrode including thin films such as a gate insulating film 205, a conducting layer 204, a mask layer 203 and an antireflection film 202 laminated on a semiconductor substrate 206 and a photoresist mask pattern 201 disposed on the antireflection film, prior to etching the mask pattern 201, plasma is generated from nitrogen gas or a mixed gas including nitrogen gas and deposition gas to subject the mask pattern 201 to a plasma curing process so as to reduce the roughness on the surface and side walls of the mask pattern 201, and then the laminated thin films 202, 203 and 204 disposed below the mask pattern 201 are subjected to a plasma etching process.

Photoresist polymers and photoresist compositions containing the same. Photoresist patterns of less than 50 nm are achieved with EUV (Extreme Ultraviolet) as an exposure light source with photoresist compositions comprising (i) a photoresist polymer comprising a polymerization repeating unit of Formula 2 or (ii) a photoresist polymer comprising a polymerization repeating unit of Formula 3 with polyvinylphenol. As a result, excellent etching resistance can be secured although the photoresist patterns have a very small thickness.wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, a, b, c, d, e, f and g are as defined in the specification.

Photoresist polymers and photoresist compositions are disclosed. A photoresist polymer comprising a polymerization repeating unit represented by Formula I is less sensitive to change in the amount of energy due to its higher active energy than that of a conventional photoresist polymer. As a result, a phenomenon where the portion of the pattern for the storage electrode contact region that receives relatively large amount of light becomes too thin is avoided when the device isolation film pattern is formed, and wherein pattern collapse caused by a high aspect ratio due to high etching resistance is prevented or avoided.whereinR1–R10, a, b, c and d are as defined in the description.

A substrate processing apparatus is provided. The apparatus includes a plurality of fluid suppliers 61, 61, 63 for supplying different processing fluids. In processing a wafer W, the substrate processing apparatus moves the fluid suppliers 61, 62, 63 along the peripheral part of the wafer W relatively. The fluid suppliers 61, 62, 63 are arranged in a direction extending from the circumference of the wafer W to its inside. With the arrangement, the apparatus is capable of stable processing of the wafer W in spite of rotating the wafer W at a low speed. Further, it is possible to improve a throughput of the apparatus in resist processing.

A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.