15000 results about "Resist" patented technology

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

Front end of line (FEOL) plasma mediated ashing processes for removing organic material from a substrate generally includes exposing the substrate to the plasma to selectively remove photoresist, implanted photoresist, polymers and / or residues from the substrate, wherein the plasma contains a ratio of active nitrogen and active oxygen that is larger than a ratio of active nitrogen and active oxygen obtainable from plasmas of gas mixtures comprising oxygen gas and nitrogen gas. The plasma exhibits high throughput while minimizing and / or preventing substrate oxidation and dopant bleaching. Plasma apparatuses are also described.

A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2 / N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr / O2 / Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr / O2 / Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle in a first orientation on a reticle support in a processing chamber, wherein the reticle comprises a metal photomask layer formed on an optically transparent substrate, and a patterned resist material deposited on the metal photomask layer, etching the metal photomask layer in the first orientation, positioning the reticle in at least a second orientation, and etching the metal photomask layer in the at least second orientation.

A resist pattern is formed on a to-be-processed film. Ions are implanted in the upper surface of the resist pattern. After ion implantation, an organic film is formed to cover the resist pattern and heated. A crosslinked resin film made of the organic film which has crosslinked is formed on the sidewall of the resist pattern by developing the organic film after heating. After formation of the crosslinked resin film, the resist pattern is removed. The to-be-processed film is processed using the crosslinked resin film as a mask.

Methods and apparatuses to improve the temperature uniformity of a workpiece being processed on a heated platen of a thermal processing station. A heated platen is enclosed in a housing incorporating an additional heat source that uniformly outputs thermal energy into the process chamber in which the heated platen is positioned. In preferred embodiments, this heat source is positioned in the lid of the housing. It is additionally preferred that the heated lid includes features that provide a gas flow path to introduce to and / or purge gas from the process chamber. In terms of photoresist performance, the improved thermal uniformity provided by using such an additional heat source in the housing, e.g., in the lid, offers improved line width control and line uniformity across a wafer.

A method of depositing a silicon oxide film on a resist pattern or etched lines formed on a substrate by plasma enhanced atomic layer deposition (PEALD) includes: providing a substrate on which a resist pattern or etched lines are formed in a PEALD reactor; controlling a temperature of a susceptor on which the substrate is placed at less than 50° C. as a deposition temperature; introducing a silicon-containing precursor and an oxygen-supplying reactant to the PEALD reactor and applying RF power therein in a cycle, while the deposition temperature is controlled substantially or nearly at a constant temperature of less than 50° C., thereby depositing a silicon oxide atomic layer on the resist pattern or etched lines; and repeating the cycle multiple times substantially or nearly at the constant temperature to deposit a silicon oxide atomic film on the resist pattern or etched lines.

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

In a coating and developing apparatus that forms a resist film on substrates such as semiconductor wafers, and develops substrates exposed by an aligner, times after the aligner unloads substrates until heating units (PEB) start heating the substrates are kept uniform. Exposed wafers are prevented from being left stagnant in an interface portion disposed between a region in which resist is coated and developed and the aligner. In the region in which resist is coated and developed, a first transferring means that successively executes transportation cycles to transfer substrates from upstream side modules to downstream side modules in a flow of processes of substrates. N heating units (PEB) are disposed (n is for example 5). Exposed wafers loaded into the heating units (PEB) are unloaded by the first transferring means after (n−1) cycles including the transferring cycle of the first transferring means have elapsed.

In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.

A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

The invention provides a display device in which parasitic capacitance associated with data lines and driving circuits is prevented using a bank layer whose primary purpose is to define areas on a substrate in which an organic semiconductor film is formed. When the organic semiconductor film for forming a luminescent element such as an electroluminescent element or an LED is formed is formed in pixel regions (7), the organic semiconductor film is formed in the areas surrounded by the bank layer (bank) formed of a black resist. The bank layer (bank) is also formed between an opposite electrode (op) and data lines (sig) for supplying an image signal to first TFTs (20) and holding capacitors (cap) in the pixel regions (7) thereby preventing parasitic capacitance associated with the data lines (sig).

There is provided a semiconductor device manufacturing method for forming a step-shaped structure in a substrate by etching the substrate having thereon a multilayer film and a photoresist film on the multilayer film and serving as an etching mask. The multilayer film is formed by alternately layering a first film having a first permittivity and a second film having a second permittivity different from the first permittivity. The method includes a first process for plasma-etching the first film by using the photoresist film as a mask; a second process for exposing the photoresist film to hydrogen-containing plasma; a third process for trimming the photoresist film; and a fourth process for etching the second film by using the trimmed photoresist film and the plasma-etched first film as a mask. The step-shaped structure is formed in the multilayer film by repeatedly performing the first process to the fourth process in this sequence.

The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate electrode including thin films such as a gate insulating film 205, a conducting layer 204, a mask layer 203 and an antireflection film 202 laminated on a semiconductor substrate 206 and a photoresist mask pattern 201 disposed on the antireflection film, prior to etching the mask pattern 201, plasma is generated from nitrogen gas or a mixed gas including nitrogen gas and deposition gas to subject the mask pattern 201 to a plasma curing process so as to reduce the roughness on the surface and side walls of the mask pattern 201, and then the laminated thin films 202, 203 and 204 disposed below the mask pattern 201 are subjected to a plasma etching process.

Photoresist polymers and photoresist compositions containing the same. Photoresist patterns of less than 50 nm are achieved with EUV (Extreme Ultraviolet) as an exposure light source with photoresist compositions comprising (i) a photoresist polymer comprising a polymerization repeating unit of Formula 2 or (ii) a photoresist polymer comprising a polymerization repeating unit of Formula 3 with polyvinylphenol. As a result, excellent etching resistance can be secured although the photoresist patterns have a very small thickness.wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, a, b, c, d, e, f and g are as defined in the specification.

Photoresist polymers and photoresist compositions are disclosed. A photoresist polymer comprising a polymerization repeating unit represented by Formula I is less sensitive to change in the amount of energy due to its higher active energy than that of a conventional photoresist polymer. As a result, a phenomenon where the portion of the pattern for the storage electrode contact region that receives relatively large amount of light becomes too thin is avoided when the device isolation film pattern is formed, and wherein pattern collapse caused by a high aspect ratio due to high etching resistance is prevented or avoided.whereinR1–R10, a, b, c and d are as defined in the description.

The present invention relates to a chemically amplified system, which is, sensitive to wavelengths between 300 nm and 100 nm, and comprises a) a polymer that is insoluble an aqueous alkaline solution and comprises at least one acid labile group, b) a compound capable of producing an acid upon radiation. The present invention comprises a polymer that is made from a alicyclic hydrocarbon olefin, an acrylate with a pendant cyclic moeity, and a cyclic anhydride. The present invention also relates to a process for imaging such a photoresist.

A photoresist cleaning solution and method for forming photoresist patterns using the same. More specifically, disclosed are a photoresist cleaning solution comprising H2o and an ionic surfactant represented by Formula 1, and a method for forming a photoresist pattern using the same. By spraying the cleaning solution of the present invention over photoresist film before and / or after exposing step, pattern formation in an undesired region caused by ghost images can be removed.

A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.

The present invention relates to photoresist monomers, polymers formed therefrom and photoresist compositions suitable for photolithography processes employing a DUV light source, such as KrF (249 nm) and ArF(193 nm); EUV; VUV; E-beam; ion-beam; and X-ray. Photoresist monomers of the present invention are represented by the following Chemical Formula 1: wherein, m is 1 or 2.Polymers of the present invention comprise repeating units derived from the comonomer of Chemical Formula 1, preferably together with monomers of the following Chemical Formula 2: wherein,R* is an acid-labile group, andl is 1 or 2.

Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

A method of forming a mask pattern includes a first pattern forming step of etching an anti-reflection coating film by using as a mask a first line portion made up of a photo resist film formed on the anti-reflection film to form a pattern including a second line portion made up of the photo resist film and the anti-reflection film; an irradiation step of irradiating the photo resist film with electrons; a silicon oxide film forming step to cover the second line portion isotropically; and an etch back step of etching back the silicon oxide film such that the silicon oxide film is removed from the top of the second line portion as sidewalls of the second line portion. The method further includes a second pattern forming step of ashing the second line portion to form a mask pattern including a third line portion made up of the silicon oxide film and remains.

A stapling cartridge having an elongated rail that provides support to a moveable clamping element and resists pulling or spreading forces caused by compressing and cutting tissue. The elongated rail can directly connect the stapling cartridge to the lower jaw and completely carry the moveable clamping element, which can couple and decouple to an anvil of an upper jaw.

Solution processible hardmasks are described that can be formed from aqueous precursor solutions comprising polyoxometal clusters and anions, such as polyatomic anions. The solution processible metal oxide layers are generally placed under relatively thin etch resist layers to provide desired etch contrast with underlying substrates and / or antireflective properties. In some embodiments, the metal oxide hardmasks can be used along with an additional hardmask and / or antireflective layers. The metal oxide hardmasks can be etched with wet or dry etching. Desirable processing improvements can be obtained with the solution processible hardmasks.