178 results about "Front end of line" patented technology

A substrate support assembly and method for supporting a substrate are provided. In at least one embodiment, the support assembly includes a body having one or more fluid conduits disposed therethrough, and a support member disposed on a first end of the body. The support member includes one or more fluid channels formed in an upper surface thereof, wherein each fluid channel is in communication with the one or more of the fluid conduits. The support assembly also includes a cooling medium source in fluid communication with the one or more fluid conduits, and a first electrode having a plurality of holes formed therethrough. The first electrode is disposed on the upper surface of the support member such that each of the plurality of holes is in fluid communication with at least one of the one or more fluid channels formed in the upper surface of the support member.

A lid assembly for semiconductor processing is provided. In at least one embodiment, the lid assembly includes a first electrode comprising an expanding section that has a gradually increasing inner diameter. The lid assembly also includes a second electrode disposed opposite the first electrode. A plasma cavity is defined between the inner diameter of the expanding section of the first electrode and a first surface of the second electrode.

A capacitive touch panel is assembled by a substrate layer, sensing layer, and surface layer. A plurality of transparent X and Y axis traces are arranged on the sensing layer and intersect each other as a matrix. A front end of each X trace and each Y trace has a joint. The plurality of X axis traces and Y axis traces are arranged at the same plane. Each X axis trace includes a plurality of induction-spots and each Y axis trace includes a plurality of induction-spots. The induction-spots of one X axis trace are connected one by one, while the induction-spots of one Y axis trace are formed separately with gaps. The adjacent induction-spots of Y axis trace are connected by a bridge structure and the induction-spots of the Y axis trace are insulated to the respective one of the plurality of X axis trace.

Structures and a method are disclosed for grounding gate-stack and / or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

A key-free mouse includes a top cover and a bottom cover connected to each other through a pivotal connection of locking pins to locking slots. The locking pins and the locking slots are respectively provided at inner side of the top and the bottom covers at front and rear ends of a longitudinal axis thereof, so that the top cover is pivotally turnable about the longitudinal axis by a predetermined degree relative to the bottom cover to actuate a left or a right switch provided in the mouse. Elastic elements such as springs are provided in the mouse separately at predetermined positions for providing the top cover with suitable supporting elasticity to recover from a pivotally turned and laterally inclined position.

A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit.

An electric rotating machine has a rotor having N and S poles and includes a stator with an annular stator core and slots. Multiple-phase stator windings are embedded in the slots, and are formed by winding continuous wires such that straight parts of the stator windings pressed in a flat shape are wound in rings around a grooved cylindrical member. The cylindrical member is inserted into a bore defined by the annular stator core so that the grooves of the cylindrical member are arranged opposite to the slots. The sets of the windings are folded back alternately outside the slots of the stator core and are wound so the sets of the windings are embedded alternately in the direction of the depth of the slots. Leading and trailing ends of the continuous wires are superposed after being wound at least one turn around the circumferentially arranged slots of the stator.

A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.

This invention relates to process sequence by high-speed atomic layer chemical vapor processing that includes deposition for diffusion barriers in the etched features on substrate followed by gap fill and subsequent in-situ removal of the blanket films on the top by plasma enhanced vapor phase processes. The apparatus and process sequences employed in these processing scheme allows the practitioner to complete all vapor phase process sequences of diffusion barrier deposition, gap fill and planarization of copper and diffusion barrier planarization. In case of copper metallization scheme, vapor phase gap fill can be employed to replace electrochemical deposition of copper and removal of copper and the diffusion barrier by vapor phase reactions can replace chemical-mechanical-polishing. Furthermore, such a processing scheme can be employed to deposit gate level dielectric layer, shallow trench isolation and also to form first metal contact plugs with a suitable barrier at the front end of line processing.

Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.

Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and / or signal connections to source / drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source / drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source / drain region and the embedded contact can extend laterally from the source / drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.

The invention provides a heat exchange plate with a streamline structure, and a printed circuit board heat exchanger with same. The first segment of the upper arc and the first segment of the lower arc of a streamline rib extend to the position of a maximum incircle from the front edge of a wing form, each first segment is a convex smooth curve, the rear end of each convex smooth curve is in tangency with the maximum incircle, second segments extend to the rear edge of the wing form from the maximum incircle, each second segment is a concave smooth curve, the front end of each concave smooth curve is in tangency with the maximum incircle, and a smooth continuous curve is formed by each first segment and the corresponding second segment at the position of the maximum incircle. According tothe heat exchange plate with a streamline structure, and the printed circuit board heat exchanger with same, because the original structure of a wing-shaped rib is redesigned and optimized, when heatexchange fluid flows through wing-shaped ribs, changes between the front part and the rear part of the maximum width of a wing-shaped rib happen more violently, and the heat exchange performance of awing-shaped channel is improved; and because structural design is carried out on the front edge and the rear edge of a wing form, the heat exchange fluid can be guided to flow better, and therefore, the pressure drop loss of the wing-shaped channels is reduced.

A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

A cable end connector assembly (1) includes a housing (2), a number of contact units (3), a spacer (4), a number of wires (5), and a cover (6). The housing includes a pair of keys (28) in a rear wall thereof. Each contact unit comprises three mating portions (32) and a U-shaped tail portion (33) opposite to the mating portion. The spacer comprises a number of through holes (400) extending therethrough, a supporting portion (42) supporting the U-shaped tail portions, and a pair of keyways (410). The supporting portion defines a number of grooves (420) in a top surface thereof. Each wire comprises a conductive core (60) received in and soldered with the tail portion. The cover is over-molded with a rear end of the housing and front ends of the wires.

It is an object of the present invention to provide a bonding structure and a copper bonding wire for semiconductor that are realizable at an inexpensive material cost, superior in a long-term reliability of a bonded portion bonded to an Al electrode, and suitable for use in a vehicle-mounted LSI. A ball-bonded portion is formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the aforementioned ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.