945 results about "Ashing" patented technology

A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH3 groups, to repair damage to the carbon-containing low-k material of the trench sidewalls and bottom caused by the trench formation process (generally etching, ashing, and wet or dry cleaning). A similar treatment, with or without the gas phase source of —CH3 groups, may be applied to repair damage caused in a subsequent planarization operation.

Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and silylation compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.

A plasma etch process for etching a porous carbon-doped silicon oxide dielectric layer using a photoresist mask is carried out first in an etch reactor by performing a fluorocarbon based etch process on the workpiece to etch exposed portions of the dielectric layer while depositing protective fluorocarbon polymer on the photoresist mask. Then, in an ashing reactor, polymer and photoresist are removed by heating the workpiece to over 100 degrees C., exposing a peripheral portion of the backside of said workpiece, and providing products from a plasma of a hydrogen process gas to reduce carbon contained in polymer and photoresist on said workpiece until the polymer has been removed from a backside of said workpiece. The process gas preferably contains both hydrogen gas and water vapor, although the primary constituent is hydrogen gas. The wafer (workpiece) backside may be exposed by extending the wafer lift pins.

A method of a single wafer wet / dry cleaning apparatus comprising:a transfer chamber having a wafer handler contained therein;a first single wafer wet cleaning chamber directly coupled to the transfer chamber; anda first single wafer ashing chamber directly coupled to the transfer chamber.

A multilevel interconnect structure is formed which uses air as a dielectric between wiring lines and which is compatible with the presence of unlanded vias in the interconnect structure. A layer of carbon is deposited over an insulating surface and then a pattern for trenches is formed in the surface of the layer of carbon. Metal is deposited in the trenches and over the layer of carbon and then a chemical mechanical polishing process is used to define wiring lines. An ashing or etch back process is performed on the carbon layer to recess its surface below the surfaces of the wiring lines. An oxide capping layer is provided over the recessed surface of the carbon and the wiring lines, for example using HSQ and curing, and then the carbon layer is consumed through the capping layer using an oxidation process. Air replaces the sacrificial carbon layer during the consumption reaction. Next, a silicon nitride etch stop layer is provided over the surface of the capping layer and then an intermetal dielectric layer is provided. A via is formed by etching through the intermetal dielectric, stopping on the etch stop layer, and then etching through the etch stop layer and the capping layer in distinct processes. The via is filled with a metal plug and then second level wiring lines are formed.