2777 results about "Oxidation process" patented technology

A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

A method for processing a substrate including a processing target layer and an organic film, include: a deposition / trimming process of forming a reinforcement film on a surface of the organic film and, at the same time, trimming a line width of a line portion of the organic film constituting an opening pattern. The deposition / trimming process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto the surface of the organic film and an oxidation process in which the line width of the organic film is trimmed while the adsorbed silicon-containing gas is converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

Perpendicular magnetic anisotropy and Hc are enhanced in magnetic devices with a Ta / M1 / M2 seed layer where M1 is preferably Ti, and M2 is preferably Cu, and including an overlying (Co / Ni)X multilayer (x is 5 to 50) that is deposited with ultra high Ar pressure of >100 sccm to minimize impinging energy that could damage (Co / Ni)X interfaces. In one'embodiment, the seed layer is subjected to one or both of a low power plasma treatment and natural oxidation process to form a more uniform interface with the (Co / Ni)X multilayer. Furthermore, an oxygen surfactant layer may be formed at one or more interfaces between adjoining (Co / Ni)X layers in the multilayer stack. Annealing at temperatures between 180° C. and 400° C. also increases Hc but the upper limit depends on whether the magnetic device is MAMR, MRAM, a hard bias structure, or a perpendicular magnetic medium.

A process for the partial catalytic oxidation of a hydrocarbon containing feed comprising contacting the feed with an oxygen-containing gas in the presence of a catalyst retained within a reaction zone in a fixed arrangement, wherein the catalyst comprises at least one catalytically active metal selected from the group consisting of silver and Group VIII elements supported on a porous ceramic carrier. The porous ceramic carrier has a distribution of total pores wherein about 70% of the total pores (1) have a volume-to-surface area (V / S) ration that is within about 20% of the mean V / S value for the total pores and no pores have a V / S ration that is greater than twice the mean V / S value for the total pores; (2) have a pore-to-pore distance between neighboring pores that is within about 25% of the mean pore-to-pore distance between neighboring pores; and (3) have a pore throat area that is within about 50% of the mean pore throat are for the pores. Additionally, about 50% of the total pores have a coordination number between neighboring pores that is within about 25% of the mean coordination number between neighboring pores. Preferably, the oxidation process comprises a multistage, staged oxygen, catalytic partial oxidation process having fewer than or equal to about five stages and including a first stage preheat temperature of greater than about 550° C., and wherein the temperature of the product mixture in each stage following the first stage is at least about 700° C.

A tandem cell or photoelectrochemical system for the cleavage of water to hydrogen and oxygen by visible light has two superimposed photocells, both cells being connected electrically. The photoactive material in the top cell is a semiconducting oxide placed in contact with an aqueous solution. This semiconducting oxide absorbs the blue and green part of the solar emission spectrum of a light source or light sources and generates with the energy collected oxygen and protons from water. The not absorbed yellow and red light transmits the top cell and enters a second photocell, the bottom cell, which is mounted, in the direction of the light behind, preferably directly behind the top cell. The bottom cell includes a dye-sensitized mesoporous photovoltaic film. The bottom cell converts the yellow, red and near infrared portion of the sunlight to drive the reduction of the protons, which are produced in the top cell during the photo catalytic water oxidation process, to hydrogen.

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Disclosed is an optimized process and apparatus for more efficiently and economically carrying out the liquid-phase oxidation of an oxidizable compound. Such liquid-phase oxidation is carried out in a bubble column reactor that provides for a highly efficient reaction at relatively low temperatures. When the oxidized compound is para-xylene and the product from the oxidation reaction is crude terephthalic acid (CTA), such CTA product can be purified and separated by more economical techniques than could be employed if the CTA were formed by a conventional high-temperature oxidation process.

A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20 / NCC / Co10Fe70B20, Co10Fe70B20 / NCC / Co10Fe70B20 / NCC, or Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk⊥(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.

The present invention provides a system and method for selectively removing organic and inorganic contaminants from plating baths. More particularly, the invented method relates to the use of a source of energy in combination with chemical oxidants, alone or in conjunction with a catalyst to oxidize organic contaminants in the plating bath to a level such that the electroplating bath can be recovered and reused after appropriate chemical adjustment. The oxidative treatment method may be a continuous process or a batch process that is performed in a single pass and the endpoint of the oxidative process detected by a sensor. Residual organics, and chloride ions in the bath are removed from the solution by a chemisorption or physisorption treatment. Inorganic contaminants are removed from the electroplating bath by selective ion exchange resins or electrodialysis, while particulate and suspended colloidal particles are removed by filtration before the treated plating bath is recycled.

A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

A catalyst for the selective oxidation of hydrogen has been developed. It comprises an inert core such as cordierite and an outer layer comprising a lithium aluminate support. The support has dispersed thereon a platinum group metal and a promoter metal, e.g. platinum and tin respectively. This catalyst is particularly effective in the selective oxidation of hydrogen in a dehydrogenation process.

Disclosed is an optimized process and apparatus for more efficiently and economically carrying out the liquid-phase oxidation of an oxidizable compound. Such liquid-phase oxidation is carried out in a bubble column reactor that provides for a highly efficient reaction at relatively low temperatures. When the oxidized compound is para-xylene and the product from the oxidation reaction is crude terephthalic acid (CTA), such CTA product can be purified and separated by more economical techniques than could be employed if the CTA were formed by a conventional high-temperature oxidation process.

Transistors are formed on the substrate having two different thickness' of gate oxides. A silicon nitride mask is used to protect one of the gate oxides while the other is grown. A nitride mask is formed from a hydrogen balanced nitride layer formed using direct plasma deposited nitride with an ammonia and silane chemistry. In one embodiment the nitride mask remains in place in the completed transistor.

Disclosed is an optimized process and apparatus for more efficiently and economically carrying out the liquid-phase oxidation of an oxidizable compound. Such liquid-phase oxidation is carried out in a bubble column reactor that provides for a highly efficient reaction at relatively low temperatures. When the oxidized compound is para-xylene and the product from the oxidation reaction is crude terephthalic acid (CTA), such CTA product can be purified and separated by more economical techniques than could be employed if the CTA were formed by a conventional high-temperature oxidation process.

A method of producing exfoliated graphite or graphene from a graphitic or carbonaceous material. The method includes: (a) dispersing a graphitic material in a liquid intercalating agent to form a suspension; and (b) subjecting the suspension to microwave or radio frequency irradiation for a length of time sufficient for producing the exfoliated graphite or graphene. In one preferred embodiment, the intercalating agent is an acid or an oxidizer, or a combination of both. The method enables production of more electrically conducting graphene sheets directly from a graphitic material without going through the chemical intercalation or oxidation procedure. The process is fast (minutes as opposed to hours or days of conventional processes), environmentally benign, and highly scalable.

The invention discloses a preparation method of a graphene material. The preparation method comprises the following steps of: with graphite carbon as a raw material, adding potassium hypermanganate and concentrated sulfuric acid in batches in different stages to control an oxidation process of graphite; adjusting the pH value of the oxidized solution to obtain graphene oxide colloidal dispersing solutions (GOS) with different concentrations; dropwise adding the GOS on the surface of a carrier or spreading out the GOS on a non-intersolubility liquid / liquid interface and drawing into a grapheneoxide thin-film (GOF); carrying out high-speed centrifugation and drying treatment on the GOS to obtain graphene oxide solid powder (GOP); reducing the GOS by selecting an appropriate reducing agent,and centrifugally drying to obtain reduced graphene solid powder (GRP); dispersing a proper amount of GRP in an organic solvent to prepare a reduced graphene oxide colloidal dispersing solution (GRS); and dropwise adding the GRS on the surface of the carrier or spreading out on the non-intersolubility liquid / liquid interface and drawing into the reduced graphene thin-film (GRF). Various graphene materials prepared by the invention are easy to mutually transform; and the concentration of the colloidal solution and the thickness of the thin-film can be controlled in a certain range.

MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source / drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source / drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

A method for forming an improved trench isolation having a conformal liner oxide and rounded top and bottom corners in the trench was achieved. The conformal liner oxide improves the CVD gap-filling capabilities for these deep submicron wide trenches, and the rounded corners improve the electrical characteristics of the devices in the adjacent device areas. After etching trenches with vertical sidewalls in the silicon substrate, a two-step oxidation process is used to form the conformal liner oxide. A first oxidation step using a low-oxygen flow rate and a low temperature (about 850 to 920 DEG C.) is used to achieve rounded bottom corners. A second oxidation step at a low-oxygen flow rate and a higher temperature (about 1000 to 1150 DEG C.) is used to achieve rounded top corners. The two-step process also results in a more conformal liner oxide. The trenches are then filled with a CVD oxide and polished or etched back to an oxidation-barrier layer / etch-stop layer over the device areas to complete the trench isolation.

One illustrative method disclosed herein includes forming a silicon / germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.

A compact portable modular wastewater treatment system which integrates several processing technologies to provide a substantially purified water source. A wastewater stream is sent through an initial filtration step. The filtered wastewater is then subjected to electrocoagulation and then further filtered. The resulting stream containing substantially only organics is then treated in an advanced oxidation process which can include passing an electrical current through the water during the oxidation process. The partially treated water is then passed through ion-exchange columns to polish ammonium and other contaminants. The ion-exchange columns are cycled through regeneration cycles to provide continuous ion-exchange medium. The ammonium rich brine solution used in regeneration is subjected to an ammonium destruct process and then reused in regenerating ion-exchange columns. The water can then be sent through a final disinfection oxidation process to destroy or inactivate pathogens and / or remove any remaining colorants or odor to provide a water source suitable for almost any use.

A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.

A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20 / NCC / Co10Fe70B20, Co10Fe70B20 / NCC / Co10Fe70B20 / NCC, or Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk⊥(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.

The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate and an etch is performed so as to form trenches within the semiconductor substrate. A shallow trench isolation structure and a method for forming a shallow trench isolation structure are disclosed. Oxidation enhancing species are then implanted into the bottom surface of the trenches and an oxidation process is performed. The oxidation enhancing species will form a deep oxidation region below the bottom surface of each trench and will form thinner oxidation regions within side surfaces of trenches. A layer of dielectric material is then deposited to fill the trenches. A chemical mechanical polishing process is performed to remove those portions of the dielectric film that overlie the hard mask. The hard mask is then removed, producing a void-free shallow trench isolation structure.

A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and / or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and / or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and / or multiple-fin FETs.

The present invention provides a system and method for selectively removing one or more organic and also preferably one or more inorganic contaminants from plating baths. More particularly, the invented method relates to the use of a source of energy in combination with chemical oxidants, alone or in conjunction with a catalyst to oxidize organic contaminants in the plating bath to a level such that the electroplating bath can be recovered and reused after appropriate chemical adjustment. The oxidative treatment method may be a continuous process or a batch process that is performed in a single pass and the endpoint of the oxidative process detected by a sensor. Residual organics, if desired, and chloride ions in the bath are removed from the solution by a chemisorption or physisorption treatment. Inorganic contaminants are removed from the electroplating bath by selective ion exchange resins or electrodialysis, while particulate and suspended colloidal particles are removed by filtration before the treated plating bath is recycled.

A multilevel interconnect structure is formed which uses air as a dielectric between wiring lines and which is compatible with the presence of unlanded vias in the interconnect structure. A layer of carbon is deposited over an insulating surface and then a pattern for trenches is formed in the surface of the layer of carbon. Metal is deposited in the trenches and over the layer of carbon and then a chemical mechanical polishing process is used to define wiring lines. An ashing or etch back process is performed on the carbon layer to recess its surface below the surfaces of the wiring lines. An oxide capping layer is provided over the recessed surface of the carbon and the wiring lines, for example using HSQ and curing, and then the carbon layer is consumed through the capping layer using an oxidation process. Air replaces the sacrificial carbon layer during the consumption reaction. Next, a silicon nitride etch stop layer is provided over the surface of the capping layer and then an intermetal dielectric layer is provided. A via is formed by etching through the intermetal dielectric, stopping on the etch stop layer, and then etching through the etch stop layer and the capping layer in distinct processes. The via is filled with a metal plug and then second level wiring lines are formed.

A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

The invention relates to a method for preparing vanadium pentoxide from sulfuric acid leach liquor of stone coal vanadium ore, particularly a method for preparing high-purity vanadium pentoxide from sulfuric acid leach liquor of low-impurity-content stone coal vanadium ore. The method is characterized by sequentially comprising the following steps: (1) extracting leach liquor, which is obtained by leaching stone coal vanadium ore with sulfuric acid, to remove impurities; (2) carrying out back extraction on sulfuric acid to carry an organic phase; (3) oxidizing the back extraction liquor; (4) carrying out hydrolysis to precipitate vanadium; and (5) calcining the vanadium precipitate slag to obtain the vanadium pentoxide. Compared with the traditional technique, by using oxydol, persulfuric acid and the like as oxidants in the oxidation process, the method provided by the invention can avoid introducing other impurity cations, thereby ensuring the purity of the product vanadium pentoxide. Compared with the traditional ammonium-salt vanadium-precipitation technique, the method provided by the invention saves the alkali consumption required by neutralization. The purity of the prepared vanadium pentoxide is up to 99.9%, and the recovery rate of vanadium is up to above 98%; and meanwhile, the invention can implement no pollution and cyclic utilization of the back extraction agent.