4972 results about "Hard mask" patented technology

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Provided is a method for patterning a substrate, comprising: forming a layer of radiation-sensitive material on a substrate; preparing a pattern in the layer of radiation-sensitive material using a lithographic process, the pattern being characterized by a critical dimension (CD) and a roughness; following the preparing the pattern, performing a CD shrink process to reduce the CD to a reduced CD; and performing a growth process to grow the reduced CD to a target CD. Roughness includes a line edge roughness (LER), a line width roughness (LWR), or both LER and LWR. Performing the CD shrink process comprises: coating the pattern with a hard mask, the coating generating a hard mask coated resist; baking the hard mask coated resist in a temperature range for a time period, the baking generating a baked coated resist; and developing the baked coated resist in deionized water.

The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a "break-through" step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

A method for providing a magnetic element is disclosed. The method includes providing at least one magnetic element layer and providing a hard mask structure for masking a portion of the at least one magnetic element layer. The hard mask structure is made from hard mask material(s) that are etchable for defining the hard mask structure. The hard mask structure also acts as a mask during definition of a width of the magnetic element. The method also includes defining the width of the magnetic element by removing a portion of the at least one magnetic element layer using the hard mask structure as a mask. The hard mask structure preferably acts as a polishing stop for a planarization step, such as a chemical mechanical polish, polishing resistant structures might be provided to improve planarization of a magnetic memory incorporating the magnetic element.

A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.

Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.

There is provided a method for manufacturing a semiconductor device including processing a substrate to be processed by using an amorphous carbon hard mask that includes processing an amorphous carbon film formed on the substrate to be processed to provide a hard mask, and forming a protective film comprising a silicon oxide film on a sidewall of the amorphous carbon film exposed during or after processing the amorphous carbon film; and the protective film preferably formed by sputtering an intermediate mask comprising at least a silicon oxide on the amorphous carbon film.

An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via. The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited. Then, via lithography and via resist pattering are performed. Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched. A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped. As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure.

A micro structure manufacture method includes the steps of: (a) preparing an etching object having an etching target film, provided with a lower hard mask layer and an upper hard mask layer stacked on the etching target film; (b) forming a resist pattern above the etching object; (c) etching the upper hard mask film by using the resist pattern as an etching mask to form an upper hard mask; (d) after the step (c), removing the resist pattern; (e) after the step (d), thinning the upper hard mask by etching; (f) etching the lower hard mask film by using the thinned upper hard mask as an etching mask to form a lower hard mask; and (g) etching the etching target film by using the upper hard mask and the lower hard mask as an etching mask, wherein the upper hard mask film is capable of being more easily etched, using the resist pattern as a mask, than the lower hard mask film. The micro structure manufacture method can etch a fine pattern with good yield.

A method of fabricating a sub-feature size pillar structure on an integrated circuit. The process first provides a substrate having formed thereon a phase change layer, an electrode layer and a hard-mask layer. Then there is formed a feature-size hard-mask, by lithographically patterning, etching and stripping a photoresist layer, followed by trimming the hard-mask to a selected sub-feature size, wherein the trimming step is highly selective between the electrode and phase change material layers and the hard-mask. The final steps are trimming the electrode and phase change layers to the size of the hard-mask and removing the hard-mask.

Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

A method and system for manufacturing a pole for a magnetic recording head. The method and system include providing an insulator and fabricating at least one hard mask on the insulator. The at least one hard mask has an aperture therein. The method and system also include removing a portion of the insulator to form a trench within the insulator. The trench is formed under the aperture. The method and system further include depositing at least one ferromagnetic material. The pole includes a portion of the ferromagnetic material within the trench.

MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.

A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the second spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.