229 results about "Stressor" patented technology

A computer implemented method and associated apparatus for the combined control of insulin bolus dosing and basal delivery for the goal of achieving normal glycemic response to meals, exercise, stressors, and other perturbations to blood glucose levels. A run-to-run algorithm is used to monitor blood glucose levels and adjust insulin delivery as conditions are varied.

A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

A structure and method for forming raised source / drain structures in a NFET device and embedded SiGe source / drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source / drain stressor in the recesses. We form a NFET S / D epitaxial Si layer over the NFET SDE regions and a PFET S / D epitaxial Si layer over PFET embedded source / drain stressor. The epitaxial Si layer over PFET embedded source / drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source / drain stressor. We perform a NFET S / D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S / D stressor Si layer to form the raised NFET source / drains.

A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source / drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.