1668 results about "Lattice constant" patented technology

Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

A multi-core holey fiber with suppression of crosstalk deterioration among transmitted optical signals in a plurality of cores, and an optical transmission system using the fiber are disclosed. The multi-core holey fiber comprises a plurality of cores arranged separately from each other, and a cladding surrounding the plurality of cores wherein the cladding has plurality of holes arranged in a triangular lattice shape to create hole layers around the plurality of cores. Additionally, d / Λ is not more than 0.5, where Λ [μm] is lattice constant of the triangular lattice, d [μm] is diameter of each of the holes; a distance between adjacent cores is equivalent to not less than six hole layers; the cores arranged farthest from the center of the multi-core holey fiber is surrounded by not less three hole layers; and the sum of the coupling coefficients between the adjacent cores is not more than 1.6×10−5 / m.

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one III-V light-emitting device including an active region including at least a portion of the second monocrystalline semiconductor layer.

A method for providing a hard bias structure is provided. The method comprises providing a seed layer for a hard bias layer, the seed layer having a seed layer lattice constant and a natural growth texture. The method further comprises depositing the hard bias layer for the hard bias structure on the seed layer, the natural growth texture corresponding to a texture for the hard bias layer. The hard bias layer has a bulk lattice constant. The step of providing the seed layer includes forming a first plasma of a first deposition gas configured to expand the seed layer lattice constant if the bulk lattice constant is greater than the seed layer constant. The step of depositing the hard bias layer includes forming a second plasma of a second deposition gas configured to expand the bulk lattice constant if the seed layer lattice constant is greater than the bulk lattice constant.

A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source / drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source / drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and / or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.