111 results about "Lattice strain" patented technology

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and / or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and / or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.

An alkali niobate-based piezoelectric / electrostrictive ceramics sintered body including, as a main crystal phase, a perovskite type oxide containing at least one type of element selected from the group consisting of Li, Na and K as A site constituent elements and at least one type of element selected from the group consisting of Nb and Ta as B site constituent elements. The number of lattice-strained layers of the piezoelectric / electrostrictive ceramics sintered body is preferably small. A diffuse scattering intensity ratio, which is a ratio of an intensity of diffuse scattering by a lattice-strained layer present near a domain wall to a sum of an X-ray diffraction intensity of a first lattice plane and that of a second lattice plane different in interplanar spacing from the first lattice plane due to crystallographic symmetry reduction is preferably 0.5 or lower.

The present invention is a method for producing a semiconductor wafer, comprising at least steps of: epitaxially growing a SiGe layer on a surface of a silicon single crystal wafer that is to be a bond wafer; implanting at least one kind of hydrogen ion and rare gas ion through the SiGe layer, so that an ion implanted layer is formed inside the bond wafer; closely contacting and bonding a surface of the SiGe layer and a surface of a base wafer through an insulator film; then performing delamination at the ion implanted layer, removing a Si layer in a delaminated layer transferred to a side of the base wafer by the delamination, so that the SiGe layer is exposed; and then subjecting the exposed SiGe layer to a heat treatment for enriching Ge under an oxidizing atmosphere and / or a heat treatment for relaxing lattice strain under a non-oxidizing atmosphere. Thereby, a method for producing a semiconductor wafer having a SiGe layer in which lattice relaxation is sufficiently performed and of which surface roughness is suppressed and of which crystallinity is good is provided.

Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germanium layer, a silicon germanium layer, and a lattice strained silicon layer formed in this order of mention onto a silicon substrate is used, while trenches are formed in the portions for device isolation regions of the semiconductor substrate by etching. Then, a silicon film is deposited on the entirety of the exposed surface, and the deposited silicon film is dry-oxidized so as to form a silicon dioxide film. As a result, the edge portions of the trenches are rounded.

A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.

An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide antimonide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.

An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide antimonide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.

The present invention provides a thin-film dielectric having a higher dielectric constant than usual ones and not requiring a special single crystal substrate, and also provides a large-capacity thin-film capacitor element using the thin-film dielectric.A BaTiO3-based perovskite solid solution and a KNbO3-based perovskite solid solution are alternately formed to form a crystal structure gradient region where a lattice constant continuously changes at the interface, and thus crystal lattice strain occurs, thereby permitting the production of a thin-film dielectric having a high dielectric constant. Also, a large-capacity thin-film capacitor element can be produced by using the thin-film dielectric of the present invention.

A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.

Lattice strain is reproducibly measured using geometric phase analysis (GPA) of a high angle annular dark field mode scanning transmission electron microscope (HAADF-STEM). Errors caused by beam shift (also known as fly-back error) between scan lines are eliminated.

Described is a method for producing a semiconductor device (100), in which at least one column-shaped or wall-shaped semiconductor device (10, 20) extending in a main direction (z) is formed on a substrate (30), wherein at least two sections (11, 13, 21, 23) of a first crystal type and one section (12, 22) of a second crystal type therebetween are formed in an active region (40), each section with a respective predetermined height (h1, h2), wherein the first and second crystal types have different lattice constants and each of the sections of the first crystal type has a lattice strain which depends on the lattice constants in the section of the second crystal type. According to the invention, at least a height (h2) of the section (12, 22) of the second crystal type and a lateral thickness (D) of the active region (40) is formed perpendicular to the main direction, in such a manner that the lattice strain in one of the sections (11) of the first crystal type also depends on the lattice constants in the other section (13) of the first crystal type. A semiconductor device (100) is also described, having at least one column-shaped or wall-shaped semiconductor element (10, 20) on a substrate (30), which can be produced in particular by means of the stated method.

A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.