33 results about "Reverse short-channel effect" patented technology

Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and / or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are / is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read / write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.

A semiconductor device including an NMOSFET which has an n-type source / drain main region containing arsenic and an n-type source / drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source / drain main region, and the concentration of the phosphorous in the source / drain buffer region is smaller than the concentration of the arsenic therein. The semiconductor device has a suppressed reverse short channel effect and reduced p-n junction leakage current. Further, the semiconductor device has a larger margin to a certain gate length and a specified threshold voltage to elevate a production yield.

Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source / drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and / or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

The invention discloses an ion implant method, comprising the following step: implanting ions according to the pre-specified ion implant sequence, wherein the sequence is as follow: germanium ions, arsenic ions, boron ions, indium ions and carbon ions. The method can effectively improve the performance of the semi-conductor components and eliminate or reduce the adverse impact of the short channel effect and / or reverse short channel effect on the semi-conductor components.

The invention relates to a high-integration, high-mobility source-drain-gate assisted junction-free transistor, which adopts two independently controlled gate electrodes, such as a source-drain control gate electrode and a gate electrode, so that the device can be guaranteed at a low doping concentration. High mobility can be achieved in the channel, avoiding the decline of device mobility and stability caused by the enhancement of random scattering effect under high doping concentration, and at the same time, a lower source can be obtained through the independent control of the source-drain control gate electrode and the gate electrode. Leakage resistance, thus effectively solving the contradiction between the increase of the source-drain resistance caused by the low doping concentration of the channel of ordinary junctionless transistors, and the high doping concentration will lead to the decrease of device mobility and stability. In addition, by adopting the groove-shaped channel design, compared with the ordinary planar structure, the effective channel length is significantly increased without increasing the additional chip area to reduce the short channel effect of the device at the deep nanoscale, so it is suitable for Promote apps.

The invention provides a method for restraining the reverse short channel effect and a manufacturing method of an NMOS (N-Channel Metal Oxide Semiconductor) device. After phosphorus ions are injected into the drain region of a shallow doping source, a fluorine ion injection procedure is added, and low-temperature annealing long-time treatment is performed on the drain region of the shallow doping source. The injected fluorine ions are combined with vacancy and interstitial atoms and the like in a grid edge area, so that the diffusion of boron elements in a P-type well region can be prevented, and the reverse short channel effect is restrained. Moreover, the fluorine ions can restrain hot carrier injection, so that the reliability of hot carrier injection does not become poor while the fluorine ions are injected.

The present invention provides an LDMOS transistor and a manufacturing method thereof. A well region is formed in a first region of a semiconductor substrate, and after the gate stack structure is formed, only ion implantation is performed on the first region of the semiconductor substrate to form at least A doped layer located in the well region, the doping type of the doped layer is opposite to that of the well region, thereby forming an asymmetric ion implantation structure on both sides of the gate stack structure, on the one hand It can increase the channel stress, improve the carrier mobility, and then increase the drive current and breakdown voltage of the device. On the other hand, it can inhibit the diffusion of dopant ions in the source region closer to the gate stack structure to the gate. In the channel region at the bottom of the stack structure, it helps to form a shallower junction, thereby reducing short channel effects and reverse short channel effects, and improving device performance.

Impurity ions are implanted into the silicon layer of an SOI substrate to achieve an ion concentration distribution which inhibits for a reduction in threshold voltage (Vth-rolloff) as a gate length is reduced. A reduction in potential barrier which runs from a drain region side is effectively inhibited to counter short channel effects resulting from a reduction in gate length attendant with miniaturization of SOI-MOSFETs.

In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.

An electronic circuit (10) comprises at least two transistors (T12, T14) coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor (T14) is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor (T12) is biased with a first gate-source voltage and a first drain-source voltage. The second transistor (T14) is biased with a second gate-source voltage and a second drain-source voltage. The first gate-source voltageand the second gate-source voltage are offset from each other by a gate-source voltage offset and the first drain-source voltage and the second drain-source voltage are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors (T12, T14) operating in different regions so that the second and third-order nonlinearities of the transistors (T12, T14) substantially cancel each other out simultaneously.