2832 results about "Doping" patented technology

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and my have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

A memory device with multiple bits per-cell. The memory device includes a side electrode; a doped semiconductor region disposed laterally in contact with a sidewall of the side electrode, such that the doped semiconductor region forms a diode, or the junction between the side electrode and the doped semiconductor region forms a diode; a layer of phase-changing material disposed laterally in contact with a sidewall of the doped semiconductor region, such that the doped semiconductor region is disposed between the layer of phase-changing material and the side electrode; and an upper electrode disposed on the layer of phase-changing material. Many storage regions can be stacked vertically, and multiple bits can be stored in one cell. Also, the contact area is reduced to a minimum dimension below the photolithographic limit.

An electronic device comprising a population of quantum dots embedded in a host matrix and a primary light source which causes the dots to emit secondary light of a selected color, and a method of making such a device. The size distribution of the quantum dots is chosen to allow light of a particular color to be emitted therefrom. The light emitted from the device may be of either a pure (monochromatic) color, or a mixed (polychromatic) color, and may consist solely of light emitted from the dots themselves, or of a mixture of light emitted from the dots and light emitted from the primary source. The dots desirably are composed of an undoped semiconductor such as CdSe, and may optionally be overcoated to increase photoluminescence.

A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

A lamp uses a solid state source to pump one or more doped semiconductor nanophosphors to produce a light output of a desired characteristic. The nanophosphor(s) is dispersed in a material, examples of which include liquids and gases. Various nanophosphors are discussed. In the examples, the material with the doped semiconductor nanophosphor(s) dispersed therein appears at least substantially clear when the lamp is off. The exemplary lamp also includes circuitry for driving the solid state source and a housing that at least encloses the drive circuitry. The lamp has a lighting industry standard lamp base mechanically connected to the housing and electrically connected to provide electricity to the circuitry for driving the solid state source.

A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types. For example, a first type of controllable region can exhibit a different doping from a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independently selected.

Methods are disclosed for producing highly doped semiconductor materials. Using the invention, one can achieve doping densities that exceed traditional, established carrier saturation limits without deleterious side effects. Additionally, highly doped semiconductor materials are disclosed, as well as improved electronic and optoelectronic devices/components using said materials. The innovative materials and processes enabled by the invention yield significant performance improvements and/or cost reductions for a wide variety of semiconductor-based microelectronic and optoelectronic devices/systems. Materials are grown in an anion-rich environment, which, in the preferred embodiment, are produced by moderate substrate temperatures during growth in an oxygen-poor environment. The materials exhibit fewer non-radiative recombination centers at higher doping concentrations than prior art materials, and the highly doped state of matter can exhibit a minority carrier lifetime dominated by radiative recombination at higher doping levels and higher majority carrier concentrations than achieved in prior art materials. Important applications enabled by these novel materials include high performance electronic or optoelectronic devices, which can be smaller and faster, yet still capture or emit light efficiently, and high performance electronics, such as transistors, which can be smaller and faster, yet cooler.

A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a semiconductor device layer in a substrate to a bottommost surface of the substrate. The shielded TSV structure includes at least one second TSV located on the outside of the first TSV and configured to laterally shield the first TSV from external electrical signals. The at least one second TSV can be a unitary cylindrical structure including the first TSV therein, or a plurality of discrete structures configured to laterally shield the first TSV with gaps thereamongst. The at least one second TSV can include a conductive material that is different from the material of the substrate, or the at least one TSV can include a doped semiconductor material that is derived from the semiconductor material within the substrate.

A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

A light emitting unit array including a plurality of micro-light emitting diodes (μ-LEDs) is provided. The micro-light emitting diodes are arranged in an array on a substrate, and each of the micro-light emitting diodes includes a reflection layer, a light emitting structure, and a light collimation structure. The light emitting structure is disposed on the reflection layer, and includes a first type doped semiconductor layer, an active layer, and a second type doped semiconductor layer that are stacked sequentially. At least a portion of the first type doped semiconductor layer, the active layer, and the second type doped semiconductor layer are sandwiched between the reflection layer and the light collimation structure.

A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.