A three-dimensional
semiconductor device, comprising a plurality of
memory cell transistors and a plurality of select transistors at least partially overlapped in the vertical direction, wherein each select
transistor comprises a first drain, an active region and a
common source formed in the substrate, distributed along the vertical direction, as well as a
metal gate distributed around the active region; wherein each
memory cell transistor comprises a channel layer distributed perpendicularly to the
substrate surface, a plurality of inter-layer insulating
layers and a plurality of
gate stack structures alternately stacked along the sidewalls of said channel layer, a second drain located on top of said channel layer; wherein said channel layer and said the first drain are electrically connected. In accordance with the three-dimensional
semiconductor memory device and manufacturing method of the present invention, the multi-gate
MOSFET is formed beneath the stack structure of the
memory cell string including
vertical channel to serve as the select
transistor, this can improve the control characteristics of the gate
threshold voltage, reduce the off-state leakage current, prevent the substrate from over-
etching, and effectively improve the reliability of the device.