603results about How to "Improve equipment reliability" patented technology

A three-dimensional semiconductor device, comprising a plurality of memory cell transistors and a plurality of select transistors at least partially overlapped in the vertical direction, wherein each select transistor comprises a first drain, an active region and a common source formed in the substrate, distributed along the vertical direction, as well as a metal gate distributed around the active region; wherein each memory cell transistor comprises a channel layer distributed perpendicularly to the substrate surface, a plurality of inter-layer insulating layers and a plurality of gate stack structures alternately stacked along the sidewalls of said channel layer, a second drain located on top of said channel layer; wherein said channel layer and said the first drain are electrically connected. In accordance with the three-dimensional semiconductor memory device and manufacturing method of the present invention, the multi-gate MOSFET is formed beneath the stack structure of the memory cell string including vertical channel to serve as the select transistor, this can improve the control characteristics of the gate threshold voltage, reduce the off-state leakage current, prevent the substrate from over-etching, and effectively improve the reliability of the device.

Conventional electrochromic devices frequently suffer from poor reliability and poor performance. Improvements are made using entirely solid and inorganic materials. Electrochromic devices are fabricated by forming an ion conducting electronically-insulating interfacial region that serves as an IC layer. In some methods, the interfacial region is formed after formation of an electrochromic and a counter electrode layer. The interfacial region contains an ion conducting electronically-insulating material along with components of the electrochromic and/or the counter electrode layer. Materials and microstructure of the electrochromic devices provide improvements in performance and reliability over conventional devices.

Methods of managing memory devices, and devices so managed. A value of a parameter, that is used to program one or more memory cells, is adapted to a monitored condition of the cell(s). Either the number of bits per cell is held fixed or the monitored condition is an intrinsic condition of the cell(s). The initial value of the parameter is optimized for those specific cells, relative to a pre-selected criterion, by programming the cell(s) in accordance with candidate values of the parameter.

PCT No. PCT/JP96/03000 Sec. 371 Date Jun. 16, 1997 Sec. 102(e) Date Jun. 16, 1997 PCT Filed Oct. 16, 1996 PCT Pub. No. WO97/14983 PCT Pub. Date Apr. 24, 1997A diffraction grating portion (12) is formed in an optical fiber (10), having a diameter of 125 mu m and serving to transmit light, along its optical axis. The optical fiber is concentrically surrounded by a lower coating portion (14) having an outer diameter of 300 mu m and consisting of a silicone resin. The lower coating portion is concentrically surrounded by a coating portion (16) having an outer diameter of 900 mu m and consisting of a liquid crystal polymer, e.g., polyester amide. The coating portion is further surrounded by an outermost coating portion (18) having an outer diameter of 1 mm and consisting of a UV curing resin colored for identification. Both the optical fiber (10) and the lower coating portion (14) have positive thermal expansion coefficients. In contrast to this, the coating portion (16) consisting of the liquid crystal polymer has a negative thermal expansion coefficient.

In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the element can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".

In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

A soft transparent adhesive layer is utilized to bond a transparent substrate material onto an AlGaInP light-emitting diode epitaxy on a GaAs substrate, and the GaAs substrate is next removed entirely. Then, a mesa etching process is performed to form a first top surface and a second top surface on the AlGaInP light-emitting diode epitaxy for respectively exposing an n-type layer and a p-type layer in the AlGaInP light-emitting diode epitaxy. Next, a metal reflective layer and a barrier layer are formed on the AlGaInP light-emitting diode epitaxy in turn, and electrodes are finally fabricated on the barrier layer.

Methods, computer program products and apparatus automate clinical NMR in vitro diagnostic analyzers. The clinical analyzer can automatically electronically monitor selected parameters and automatically electronically adjust parameters to maintain the analyzer within desired operational ranges. The clinical NMR analyzers can be configured as a networked system with a plurality of clinical NMR analyzers located at different use sites; and at least one remote control system in communication with one or a plurality of clinical NMR analyzers, the at least one remote system configured to monitor selected local operating parameters associated with a respective clinical NMR analyzer.