5279 results about "Reference current" patented technology

A method for making a laser driver circuit for burst mode is described. The method includes the following steps: First, a continuous mode laser driver circuit is selected, the chip having a temperature compensation output, a bias current setting input, and a reference current setting input. Next, the temperature compensation signal is converted to a reference current setting signal via a first bias adjustment circuit, and the reference current setting signal is input to the reference current setting input. Then, the bias current setting input is connected to ground via a second bias adjustment circuit. The reference current setting signal automatically adjusts the high level and the low level of the eye diagram of the laser according to the environmental temperature, so that the high level and the low level are kept stable to reduce the bit error rate in transmission.

An adaptive current limiter including a conversion network and an amplifier network developing an adaptive current limit signal for use by a switching regulator to limit peak current through an inductor of the switching regulator. The switching regulator develops a pulse control signal for controlling switching of current through the inductor to convert an input voltage to an output voltage. The conversion network provides a limit value by applying a duty cycle of the pulse control signal to a reference value. The amplifier network is configured to develop the adaptive current limit signal based on the limit value. The conversion network may multiply the reference value by the duty cycle to develop the limit value. The amplifier network may include a current source providing a fixed reference current to an amplifier to establish a minimum level of the adaptive current limit signal.

To provide a source driver circuit for an EL display panel with reduced variations in output current. A source driver circuit contains unit transistors 634 each of which constitutes a single unit. The 0th bit consists of one unit transistor 634, the 1st bit consists of two unit transistors 634, the 2nd bit consists of four unit transistors 634, the 3rd bit consists of eight unit transistors 634, the 4th bit consists of 16 unit transistors 634, and the 5th bit consists of 32 unit transistors 634. Each unit transistor 634 composes a current mirror circuit in conjunction with a transistor 633a. Regulating the current Ib flowing through the transistor 633a allows for changing the current flowing through the unit transistors 634. Accurate source driver IC with small variations can be provided by configuring output current circuits with unit transistors and regulating reference currents so that the output current of the unit transistors can be regulated.

A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

A power converting device includes a single-phase multiplex converter used as an active filter and a control device. The single-phase multiplex converter includes multiple single-phase inverters connected in series at AC output sides. Each of the single-phase inverters converts DC power fed from a DC power supply into AC power. The control device includes hysteresis comparators and controls output voltage of the single-phase multiplex converter by gradational output voltage control, based on the sum of selectively combined output voltages of the multiple single-phase inverters. The control device controls the single-phase multiplex converter so that an output current follows a harmonic compensation reference current, canceling harmonics leaking from a load to which the power converting device is connected.

One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.

A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence / non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

A circuit for providing power factor correction includes a boost converter circuit with a boost inductance and a power factor correction switch and a control circuit. The control circuit provides a pulse width modulated signal to control the on time of a PFC switch, and also includes a power factor correction pulse width modulated device receiving as inputs a rectified AC input voltage, a DC bus voltage, a signal proportional to the current through the inductor and a reference current signal. The power factor correction pulse width modulated device also includes a pulse width modulated generator operable to provide the pulse width modulated signal to control the on time of the PFC circuit and a pulse width modulated blanking device operable to provide an enable / disable signal to disable the pulse width modulated generator when predetermined conditions are met.