4116 results about "Gate driver" patented technology

A programmable power (PPSE) switching element including a front power transistor, a main switching transistor, and at least one reverse current blocking transistor in series, a gate of each of which is connected to a gate driver; an inductor and a shunt resistor connected in series with the transistors; a charge storage capacitor connected between ground and a junction located between the inductor and the shunt resistor; a high-speed NPN transistor, a collector of which is connected to the front power transistor and an emitter of which is connected to an output of the main switching transistor via the shunt resistor; a current measurement element in parallel to the shunt resistor; a voltage amplifier; and a high-speed MCU.

A display device having touch sensors and a method of driving the same are disclosed. The display device includes a display panel including a pixel array including pixels and a touch sensor array including touch sensors formed in the pixel array, the pixel array being divided into blocks, a gate driver to sequentially drive a plurality of gate lines in the pixel array in a block unit, a data driver to drive a plurality of data lines in the pixel array when the gate lines are driven, a touch controller to sequentially drive the touch sensor arrays in the block unit, and a timing controller to divide one frame into at least one display mode at which the pixel array is driven and at least one touch sensing mode at which the touch sensor array is driven and to control the gate drive, the data driver and the touch controller so that the display mode and the touch sensing mode alternate.

A current source generates, with high efficiency, a current that is substantially constant over a wide range of output voltages. This current is injected into the first end of a series-connected string (hereinafter referred to as string) of LEDs, with the second end of the string connected through a resistor to ground. The voltage developed across this resistor, which is a measure of current flow in the series string, is fed back to the current source, wherein feedback maintains nearly constant current output over a wide range of output voltages. A switch, such as a field effect transistor (FET) is placed in parallel with each LED in the string. A level shift gate driver couples a pulse width modulated control signal to the gate of each FET. When the FET across a particular LED is on, substantially all the current flows through the FET rather than the LED, and little or no light is emitted. Because the one resistance of the FET is very low, the power dissipated in the FET (current squared times resistance) is also very low. With the FET turned on, the forward voltage drop of the LED it is controlling drops to near zero, since little current is flowing through the LED. However, because the current source is designed to provide constant current over a wide range of output voltages, the current flow through the other LEDs in the series string changes little. When the FET is turned off, substantially all of the current flows through the associated LED, turning it on. By modulating the duty cycle of each FET, the brightness of each associated LED may be varied smoothly over its full range.

An electro-luminescence display device, including gate lines, data lines crossing the gate lines, pixel cells at crossings of the gate lines and the data lines, a gate driver that sequentially applies a gate signal to the gate lines during one horizontal period, and a plurality of data driving circuits that apply voltage signals to the pixel cells along a gate line during a first time of the horizontal period and applying current signals to the pixel cells during a second time after the first time of the horizontal period.

A driving circuit in an organic electroluminescent device includes a gate driver unit for sequentially outputting a control signal to select gate lines in a luminescent array unit and a current driver unit for supplying picture data to a data lines in the luminescent array unit corresponding to the gate lines selected by the gate driver unit and selectively driving organic electroluminescent devices of the selected line. The driving circuit includes a minimum gray level judgment unit for determining whether the picture data is of a predetermined minimum gray level; and a switching unit for receiving a control signal according to the determination made by the minimum gray level judgment unit and for selectively supplying a reference voltage or a reference current to the selectively driven organic electroluminescent devices.

An EL display device includes: a source driver circuit to output a video signal voltage; a gate driver circuit to select a pixel in a display screen; a first capacitor to maintain the video signal voltage; and a drive transistor to supply current to an EL element of a pixel. The video signal voltage is applied to the drive transistor to perform a predetermined operation, and written into the first capacitor. The video signal voltage maintained in the first capacitor is used to perform an offset cancel operation.

A protection circuit for a boost power converter provides input under-voltage protection and output over-voltage and over-current protection. The protection circuit includes a control power MOSFET connected in series between the ground of the boost power converter and the ground of the load. The arrangement of the circuit makes it easy to drive the gate of an N-channel power MOSFET and is ideal for current-limiting control, which utilizes the Rds-on of the MOSFET as a current sensing element. Neither a specific gate-driver nor a current sensing resistor is required, and thus high efficiency can be achieved. Furthermore, the slow slew-rate at the gate of the MOSFET provides a soft-start to the load. The protection circuit includes a temperature compensation circuitry to offset the variation of the Rds-on. A time delay circuit prevents the switching elements and protection elements from overload damage.

A display apparatus comprises a liquid crystal display panel, gate driver circuit for scanning gate lines of the display panel, drain driver circuit for supplying the display data to drain lines of the display panel, level modulator circuit coupled to the display panel and control circuit. The control circuit determines that video data represents a still image data, stoped the operation of the drain driver circuit and activates the level modulator circuit. The level modulator circuit reads out from display signals from the display panel and re-writes display signals to the display panel in order to display the still image on the display panel. In this manner, the electric power consumed by the drain circuit can be conserved when the display apparatus displays the still image.

An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

An apparatus for driving a liquid crystal display device includes a liquid crystal display panel having liquid crystal cells in respective regions defined by a plurality of gate and data lines, a data driver providing video signals to the data lines, a gate driver providing scan signals to the gate lines, a timing controller controlling the gate and data drivers, and generates a plurality of dimming signals by resetting a dimming curve in accordance with input data, and a light emitting diode backlight unit driving light emitting diode groups in accordance with the plurality of dimming signals to provide light to the liquid crystal display panel.

The display matrix section 200 has pixel circuits 210 arranged in the form of a matrix, a plurality of gate lines Y1, Y2 . . . that extend in the row direction, and a plurality of data lines X1, X2 . . . that extend in the column direction. The scan lines are connected to a gate driver 300, and the data lines are connected to a data line driver 400. A pre-charging circuit 600 or additional current generation circuit is installed for each data line as means for accelerating the charging or discharging of the data line. For each data line, charging or discharging is accelerated by pre-charging or current addition prior to the completion of the setting of the light emission level in the corresponding pixel circuit 210.

An apparatus is provided which integrates sensor functionality with an active matrix display such as an AMLCD. A conventional active matrix 6 of LCD pixels 10 is provided with standard display source and gate drivers 4 and 5. The display source driver 4 supplies data signals for generating the required pixel response to column electrodes 12 which are also connected to an output arrangement 19 including sense amplifiers 20. During a display phase of operation, the AMLCD operates conventionally with the matrix 6 being refreshed a row at a time and frame by frame. Between frames, the sense amplifiers 20 are enabled and the matrix 6 is again scanned by the gate driver 5. The characteristics of each pixel represent an external stimulus which is sensed by the relevant sense amplifier 20 and supplied at an output 23 of the arrangement.

A source driver outputs a data signal and a reset (black) signal alternately to a source line. Four-hundred and eighty gate lines are divided into three groups each comprising 160 lines, and connected to gate drivers. A display control section outputs a discriminant signal, a scan start signal and a clock signal to the gate drivers, where the nth gate line is selected with the data signal outputted by the source driver, and where the (n+160)th gate line is selected with the reset signal outputted. Further, n is shifted sequentially. By writing the reset signal during the latter ⅓ of one frame like this, light leakage of pixels that are changed over from white display to black display is eliminated. Also, blurs of edge portions of a motion picture are reduced. Thus, display grade for motion pictures is enhanced with a minimum improvement.

Apparatus and system for powering an isolated gate driver. In one embodiment, the apparatus comprises a gate driver power supply unit (PSU), coupled to a transistor and to an isolated gate driver that couples control signals to the transistor, for (i) harnessing energy from commutation action across the transistor, and (ii) using the harnessed energy to power the isolated gate driver.

A display apparatus includes: a substrate including display areas and a non-display area disposed around edges of the display areas; gate lines disposed in the display areas; data lines disposed in the display areas and crossing the gate lines; pixels disposed in the display areas and connected to the gate lines and data lines; and a gate driver disposed in the peripheral area, between the display areas. The gate driver is connected to the gate lines, to output gate signals to the gate lines.

System and method for adjusting a threshold of a power conversion system. The system includes a threshold generator configured to receive a first signal and generate a threshold signal based on at least information associated with the first signal, a comparator configured to receive the threshold signal and a second signal and generate a comparison signal, and a gate driver configured to generate a drive signal based on at least information associated with the comparison signal. The gate driver is coupled to at least a switch configured to receive the drive signal and affect a current flowing through a primary winding coupled to a secondary winding. If the second signal is larger than the threshold signal in magnitude, the drive signal causes the switch to open. The drive signal is associated with a switching frequency.

The invention discloses a wireless multi-charger system capable of saving the total charging time of a large number of wireless power transmission devices since one wireless multi-power transmission device includes a plurality of the wireless power transmission devices so that a large number of the wireless power transmission devices can be charged with electricity, and preventing the damage of the wireless power transmission devices and the wireless multi-power transmission device although foreign substances are put on charger blocks that are not charged. The wireless multi-charger system (A) according to the present invention includes an external body formed as a wireless charger case (11), wherein the wireless charger case has a wireless charger table (12) formed in an upper surface thereof, wherein the wireless charger table has a plurality of charger blocks (14), each of which includes a primary charging core (13), wherein the full-bridge resonant converter is present in a plural form and coupled respectively to a plurality of the charger blocks, wherein a multi-gate driver module is provided to transmit a converted power signal to each of a plurality of the full-bridge resonant converters under the control of the central controller, and wherein a reception signal processor module is coupled to a plurality of the charger blocks for processing a signal transmitted from the wireless power transmission device (30) and supplies the processed signal to the central controller.

A liquid crystal display device (LCD) includes a liquid crystal panel having a plurality of gate lines, a plurality of data lines, and a plurality of common voltage supply lines, the liquid crystal panel being divided into a plurality of blocks, a plurality of gate driver integrated circuits (ICs) connected to the plurality of gate lines, a plurality of data driver ICs connected to the plurality of data lines, and a plurality of common voltage compensators to supply compensated common voltages to the common voltage supply lines the corresponding blocks.

A DC-DC converter includes a power switching device and a mode control logic circuit to control the power switching device and generate an ON-pulse. A flip-flop is configured to be set by the mode control logic circuit. A current mode comparator is configured to reset the flip-flop and to compare a signal based upon current flowing through the power switching device with a signal based upon an output voltage of the dual mode flyback DC-DC converter. A transformer is driven by the current mode comparator. The mode control logic circuit includes a timer starting when a gate driver control signal applied to the power switching device turns the power switching device off and configured to generate a pulse when an off time interval elapses, a zero current detector circuit configured to sense a voltage on the transformer and generate a pulse when the voltage drops below a trigger threshold, and a combinatory logic circuit configured to compare pulse signals generated by the timer and the zero current detector circuit and generate the ON-pulse based thereupon.

A display device including a panel having a display area and first, second, third and fourth non-display areas formed at an outer portion of the display area, said first non-display area facing the second non-display area, and the third non-display area facing the fourth non-display area; a data driver disposed in the first non-display area, and configured to drive a plurality of data lines provided in a first direction in the display area; a gate driver disposed in the second non-display area and configured to drive a plurality of gate lines provided in a second direction vertical to the first direction in the display area; a timing controller configured to drive the data driver and the gate driver; and a plurality of link lines in the display area and extending from the gate driver and provided in parallel to the data lines respectively connected to the gate lines.

A converter has a transformer with primary and secondary windings each having n coils in a series-series arrangement connected to primary and secondary sides. The primary side has n primary legs each having a top switch and a bottom switch and connected to the primary winding therebetween. The secondary side has n secondary legs, each secondary leg has a synchronous rectifier switch and an output filter inductor connected to the secondary winding therebetween. A complimentary control for the primary side comprising a gate driver transformer with primary winding in series with a DC blocking capacitor connected to a drain and a source of the top switch of each primary leg, and a gate drive transformer, for each primary leg, with secondary winding containing a leakage inductor and in series with a DC blocking capacitor and a damping resistor connected to gate and source of the secondary side synchronous rectifier.