33827 results about "Data lines" patented technology

A data path for coupling data between a memory cell and an input / output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

The present invention provides a reflective type liquid crystal display device and fabricating method thereof, by which resolution is enhanced in a manner of representing two colors from one sub-pixel. The present invention includes a first substrate having a plurality of thin film transistors and a plurality of pixel electrodes within a plurality of sub-pixels defined by a plurality of gate and data lines perpendicularly crossing with each other, respectively, a second substrate assembled to the first substrate to confront, a liquid crystal layer between the first and second substrates, a third substrate assembled to the first substrate to confront, a plurality of reflective electrodes on an inside of the third substrate to correspond to a plurality of the sub-pixels, respectively, and a color filter layer having a plurality of electrophoretic bodies on a plurality of the reflective electrodes wherein each of the electrophoretic bodies is micro-encapsulated with ionic pigment particles.

A liquid crystal device includes a scanning line driving circuit, a data line driving circuit, a first VDD power supply wiring line that supplies power to the data line driving circuit, a second VDD power supply wiring line that supplies power to the scanning line driving circuit, and a common wiring line that electrically connects the first VDD power supply wiring line and the second VDD power supply wiring line to each other in an integrated manner. The common wiring line includes electrical conductors, a wiring line, and contact holes.

Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided.

A stacked DRAM memory chip for a Dual In Line Memory Module (DIMM) is disclosed. According to one aspect, the DRAM memory chip comprises at least four stacked DRAM memory dies. Further, the memory dies are each selectable by a corresponding internal memory rank signal. Each memory die comprises an array of memory cells. A common internal address bus is provided for addressing the memory cells and is connected to all stacked DRAM memory dies. Internal data buses are provided for writing data into the memory cells and reading data out of the memory cells of the DRAM memory dies. An integrated redriving unit comprises buffers for all internal address lines provided for driving external address signals applied to address pads of the DRAM memory chip. A multiplexer / demultiplexer switches the internal data lines of the selected DRAM memory die. A memory rank decoder selects a corresponding memory die.

An electronic apparatus includes unit circuits provided with electronic devices, data lines connected to the unit circuits, a first output device to output, as a first output, a current or a voltage corresponding to an externally supplied data signal, a second output device to output, as a second output, a current or a voltage corresponding to the magnitude of the first output, and a selection supply device to select one of or both the first output from the first output device and the second output from the second output device and to supply the selected output to the data line. With this configuration, the image reproducibility in a low-luminance / low-grayscale display area of a display apparatus using EL devices is enhanced.

A pixel driver circuit for driving a light-emitting element and a pixel circuit having the pixel driver circuit are provided. The pixel driver circuit includes a data line, address lines, switch thin film transistors, feedback thin film transistors and drive thin film transistors. The pixel circuit may include an organic light emitting diode, which is driven by the pixel driver circuit.

The invention provides a method for implementing a multi-level display of an electro-optical device according to a time ratio gray-scale method without providing reset lines. In an electro-optical device that includes, at an intersection of a scanning line and a data line, an electro-optical element, a driving transistor that drives the electro-optical element, and a switching transistor that controls the driving transistor, a gray-scale is obtained by performing a plurality of set-reset operations. Each set-reset operation includes: a setting step of supplying an on-signal to the switching transistor via the scanning line, and of supplying a set signal to select a conducting state or a non-conducting state of the driving transistor to the driving transistor via the data line and the switching transistor in accordance with the one signal; and a resetting step of supplying an on-signal to the switching transistor via the scanning line, and of supplying a reset signal to select the non-conducting state of the driving transistor to the driving transistor via the data line and the switching transistor in accordance with the one signal.

A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.