25459 results about "Input/output" patented technology

Systems and methods for navigating hypermedia using multiple coordinated input / output device sets. Disclosed systems and methods allow a user and / or an author to control what resources are presented on which device sets (whether they are integrated or not), and provide for coordinating browsing activities to enable such a user interface to be employed across multiple independent systems. Disclosed systems and methods also support new and enriched aspects and applications of hypermedia browsing and related business activities.

A system for processing semiconductor substrates includes a front-end with at least two vertical levels of input / output ports for transferring substrate cassettes into or out of the housing of the processing system. The front-end also includes at least one level of storage positions, e.g., two levels of storage positions, which can be disposed between the two vertical levels of the input / output ports. The two vertical levels of storage positions can each be provided with two storage positions and each of two levels of input / output ports can be provided with accommodations for two cassettes, allowing for a total of eight cassettes to be accommodated at the front-end of the processing system. Inside the housing of the processing system, interior storage positions can be provided adjacent a wafer handling chamber and spaced apart from a cassette store having rotary platforms for housing cassettes. A single cassette handler can be used to access cassettes at each of the input / output ports and the interior storage positions.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.