22015 results about "Chip" patented technology

An electroluminescent device having a plurality of current driven pixels arranged in rows and columns, such that when current is provided to a pixel it produces light, including each pixel having first and second electrodes and current responsive electroluminescent media disposed between the first and second electrodes; at least one chiplet having a thickness less than 20 micrometers; including transistor drive circuitry for controlling the operation of at least four pixels, the chiplet being mounted on a substrate and having connection pads; a planarization layer disposed over at least a portion of the chiplet; a first conductive layer over the planarization layer and connected to at least one of the connection pads; and a structure for providing electrical signals through the first conductive layer and at least one of the connection pads of the chiplet so that the transistor drive circuitry of the chiplet controls current to the four pixels.

A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.

Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

The system generally includes a crosspoint switch in the local data collection system having multiple inputs and multiple outputs including a first input connected to the first sensor and a second input connected to the second sensor. The multiple outputs include a first output and a second output configured to be switchable between a condition in which the first output is configured to switch between delivery of the first sensor signal and the second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal from the first output and the second sensor signal from the second output. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. Unassigned outputs are configured to be switched off producing a high-impedance state. The local data collection system includes multiple multiplexing units and multiple data acquisition units receiving multiple data streams from multiple machines in the industrial environment. The local data collection system includes distributed complex programmable hardware device (CPLD) chips each dedicated to a data bus for logic control of the multiple multiplexing units and the multiple data acquisition units that receive the multiple data streams from the multiple machines in the industrial environment. The local data collection system is configured to manage data collection bands.

A vapor sensing device that is sufficiently small and lightweight to be handheld, and also modular so as to allow the device to be conveniently adapted for use in sensing the presence and concentration of a wide variety of specified vapors. The device provides these benefits using a sensor module that incorporates a sample chamber and a plurality of sensors located on a chip releasably carried within or adjacent to the sample chamber. Optionally, the sensor module can be configured to be releasably plugged into a receptacle formed in the device. Vapors are directed to pass through the sample chamber, whereupon the sensors provide a distinct combination of electrical signals in response to each. The sensors of the sensor module can take the form of chemically sensitive resistors having resistances that vary according to the identity and concentration of an adjacent vapor. These chemically sensitive resistors can each be connected in series with a reference resistor, between a reference voltage and ground, such that an analog signal is established for each chemically sensitive resistor. The resulting analog signals are supplied to an analog-to-digital converter, to produce corresponding digital signals. These digital signals are appropriately analyzed for vapor identification. The device can then subsequently transmit the digital signals over a computer network, such as the Internet, for analysis at a remote location.

Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

The invention discloses an IEEE 1588 time synchronization system. By adding a time-stamp processing module, a time-stamp message transceiving sub module, a time-stamp message resolving sub module, a time-stamp message generating sub module, a local time recording register, and an RTC correction / time read-write module in the module are used for combining peripheral components such as a switch module, a PHY and a real-time clock (RTC) module to form a hardware system. When in use, the high precision time synchronization requested by an IEEE 1588v2 protocol can be implemented by using the modes of one-to-one or one-to-many of master-slave synchronization. The invention also discloses a method for implementing the IEEE 1588 time synchronization, which can implement the function of the time synchronization system by processing the time information of master-slave devices in real time. The invention plays an active role in promoting Ethernet construction.

A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip. The apparatus, servicing a plurality of internal scan chains wherein the number of said internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, includes: a) logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs, and converting the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values provided by the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit position at a time; wherein a first plurality of the input data words supplied to the primary inputs produce a second plurality of expanded data words that are loaded into the internal scan chains to achieve an improved test coverage.

Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit.

A a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

Significant advances in semiconductor microelectronics technologies have resulted in greatly enhanced chip performance. Systems studies have continuously shown that on-board interconnects between chips are the bottleneck in achieving board level performance that is comparable with this chip performance. This invention provides a multiple-layer photonic-electronic circuit board family that solves this interconnect performance problem. Multiple layers of patterned optical channel waveguides and patterned electrical conductors co-exist in a single circuit board structure, with optical vias to transport light between different photonics layers and electrical vias to transport electrical signals and power between different electronics layers. An all-lithographic fabrication technology is used to build the entire board structure with mutually compatible planar processing steps. Novel techniques are used to produce channel optical waveguides connected to in-plane 45 degree turning mirrors and channel optical waveguides connected to optical vias with out-of-plane 45 degree turning mirrors. The mirrors can have either total internal reflection or metallized facets.