A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and
troubleshooting capability for functional logic implemented within
field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a
system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test
multiplexer is used to provide real-time output to test pins for use with external
test equipment. By retrieving the hardware snapshot information with a trace program running on a
system in which the FPGA is used,
software and hardware debugging are coordinated, providing a sophisticated model of overall
system behavior. Special test circuits are implemented within the test logic configurations to enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators are used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.