1400 results about "Gigabit" patented technology

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

A point-to-point, wireless, millimeter wave communications link between two stations at least one of which is a mobile station. A millimeter wave transmitter system operating at frequencies higher than 57 GHz with a tracking antenna producing a beam having a half-power beam width of about 2 degrees or less and a millimeter wave receiver also with a tracking antenna having a half-power beam width of about 2 degrees or less. In preferred embodiments each mobile station has a global position system (GPS) and a radio transmitter and both tracking antennas are pointed utilizing GPS information from the mobile station or stations. The GPS information preferably is transmitted via a low frequency, low data rate radio. Each millimeter wave unit is capable of transmitting and / or receiving, through the atmosphere, digital information to / from the other station at rates in excess of 155 million bits per second during normal weather conditions. In preferred embodiments actually built and tested by Applicants digital information has been transmitted at rates of 1.25 gigabits per second. Preferred communication links described here are millimeter wave links operating at frequencies of 71-73 GHz and 74-76 GHz mounted on simple two-axis gimbals. Pointing information of the required accuracy is provided by GPS receivers and standard radio links which send the GPS calculated positions to the millimeter wave systems at the opposite end of the link. In these embodiments there is no need for any complicated closed loop pointing information derived from received signal intensity or phase. On moving platforms locally generated inertial attitude information is combined with the GPS positions to control pointing of the gimbaled transceivers.

The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.

The present invention describes a method and apparatus to effectively manage data buffers for a client and a server connection in a multiple connection environment. The TCP processes of servers and clients are merged into an independent TCP process in a TCP ‘proxy’ server. The TCP proxy server includes a control unit and a data switching unit (the proxy application). The TCP proxy server terminates the client TCP connection and initiates a separate TCP connection with the server. The data switching unit binds the two individual connections. The TCP proxy server portrays the actual server TCP. The control unit in the TCP proxy server manages data buffers, control memory and supports multiple connections. The control unit ‘pushes’ the data into the buffers by monitoring the use of the buffers. The control unit does not wait for data requests from the data switching unit thus, eliminating the overhead of data request messages.

A wireless system includes a transmitter with a baseband processor responsive to groups of transmitter antenna arrays for communicating over directional beams; and a receiver with a baseband processor responsive to groups of receiver antenna rays for communicating with the transmitter over the directional beams, the receiver including both a rank adaptation providing a transmit mode feedback to the transmitter and a blind beamforming providing a transmit beamformer index feedback to the transmitter and receiver groups of antenna arrays.

This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK / AM is described first, followed by the ASK / AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM / IQ demodulator system concept and the FSK / FM detector circuit details.

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network / switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support / mounting members, which in turn are mounted to a rack and / or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links. The communication links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.

An optical transceiver for converting and coupling an information-containing electrical signal with an optical fiber including a housing having an electrical connector with a plurality of XFI electrical interfaces for coupling with an external electrical cable or information system device and for transmitting and / or receiving an information-containing electrical signal having a data rate of at least 10 Gigabits per second on each interface, and a fiber optic connector adapted for coupling with an external optical fiber for transmitting and / or receiving an optical communications signal having a data rate at least 40 Gigabits per second; and at least one electro-optical subassembly in the housing for converting between an information-containing electrical signal and a modulated optical signal corresponding to the electrical signals.

One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'd blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.

A combination of a wet mate electrical connector and a gigabit miniature transceiver in a pressure resistant cable plug connector assembly. The cable plug connector assembly includes a wet mate connector, a miniature gigabit transceiver, and electrical and optical connections necessary to convert transmitted electrical data signals to optical data signals and vice versa.

A memory access processor and memory access interface for transferring data information to and from a plurality of SSRAM locations. The processor has a lookup controller for identifying a data request and locating the data requested from the SSRAM locations. The bus allows a data request and retrieval throughput from a routing processor to the memory access processor at a maximum rate, about 10 gigabits per second without substantial pipeline stalls or overflows.