An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed
data signal. By using the buffers and registers, the incoming
signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming
data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable
communication link and will also provide a less expensive solution for
serialization / deserialization. The present invention includes a
serializer that receives parallel
data input from a computer and serializes the data for transmission over a high-speed
serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer
system on the receiving end. By utilizing two related
clock signals, one
clock signal being an integer multiple of the other, a self-
synchronizing serializer / deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel
signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a
Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.