562 results about "Adder" patented technology

A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data. Each one of the full adders has a summation output, a carry bit input and a carry bit output. The method includes adding in each one of the full adders: (a) a corresponding bit of plural bit input data provided by the director; (b) the corresponding one of the bits of the plural bit read data; and, (c) a carry bit fed the carry bit input from a preceding full adder. Each one of the full adders provides: (a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and, (b) a bit on the summation output representative of a least significant bit produced by the full adder. The bit on the summation output is stored in a corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, the carry bit produced from one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director providing a full adder for each one of the bits of the plural bit read stored. The full adder has a carry bit input and a carry bit output. The method includes adding each one of a bits of plural bit input data provided by the director with a corresponding one of the bits of the plural bit read data in the provided full adder together with a carry bit fed the carry bit input of such provided full adder. The full adder provides: a carry output bit; and, a summation of the bits fed to such provided full adder to the corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, a carry bit produced by one full adder provided for a lower order bit of the plural bit read data to the carry bit input of a second full adder provided by for next, successive higher order bit of the plural bit read data selectively in accordance with one of a plurality of bits of a carry bit mask provided by the director.

To provide an intra prediction apparatus which can circumvent a hazard problem and improve the time reduction effect. An intra prediction apparatus 11 performs intra predictions of a picture. The intra predictions include: second intra predictions of respective second blocks (blocks) which are obtained by dividing a first pixel block; and a first intra prediction of the first block (macroblock) which constitutes the picture. The intra prediction apparatus 11 includes: an intra prediction unit (a prediction unit 113, an orthogonal transform and quantization unit 115, an inverse orthogonal transform and inverse quantization unit 116, and an adder 117) which performs the intra predictions; and a control unit 119 which controls the intra prediction unit to perform in parallel the intra prediction of the macroblock and the intra predictions of the respective pixel blocks.

A 100Base-TX receiver employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal. The FIR filter includes three delay stages, each delaying the input signal with an 8 ns delay (the period of one data cycle of the MLT-3 input signal), a set of three amplifiers for amplifying the delay stage outputs with gains C1, C2 and C3, and a summer for summing the outputs of the three amplifiers to produce a compensated, equalized MLT-3 signal. A low-pass filter filters the FIR filter output signal, and a data slicer digitizes the low-pass filter output during each data cycle to produce data representing the incoming MLT-3 as having one of six levels. An adaptive control signal processes the slicer output data to determine how to set the gains C1, C2 and C3 of the three FIR amplifiers to provide the correct amount of equalization and compensation. The adaptive control circuit also processes the slice data to adaptively adjust the phase of a clock signal controlling timing of the data slicer, to adaptively adjust an amount of baseline wander compensation provided to the MLT-3 signal, and to determine the value of data conveyed by the MLT-3 input signal.

An adder unit (60e) reads a desired CGH pattern from a pattern memory unit (60a) and a phase distortion correction pattern from a distortion-correction pattern memory unit (60d) and adds both patterns together to generate a phase distortion corrected pattern. A control unit (60g) controls a phase modulation module (40) in accordance with the phase distortion corrected pattern. Accordingly, phase-modulated light based on the desired phase pattern can be generated precisely, easily and quickly.

A filtering apparatus in a hardware random number generator that prevents the random number generator (RNG) from outputting a contiguous string of zeros or ones longer than a specified length. The maximum length is programmable in the apparatus. The apparatus includes a counter that keeps a current count of contiguous zero bits in a series of bytes generated by the RNG. An adder generates a sum of the current zero bit count and the number of leading zeros in the next byte generated. If the sum exceeds the maximum length, then the filter throws out the byte rather than accumulating it. Otherwise, if the byte contains all zeros, the counter is updated with the sum; or if the byte contains trailing zeros, the counter is updated with the number of trailing zeros; otherwise the counter is cleared. The apparatus does the same for contiguous one bits.

A circuit for calculating a sum of products, each product having a q-bit binary operand and a k-bit binary operand, where k is a multiple of q,includes a q-input carry-save adder (CSA); a multiplexer (10) by input of the adder, having four k-bit channels respectively receiving the value 0, a first (Yi) of the k-bit operands, the second k-bit operand (M[63:0], mi), and the sum of the two k-bit operands, the output of a multiplexer of rank t (where t is between 0 and q−1) being taken into account by the adder with a t-bit left shift; and each multiplexer having first and second path selection inputs, the bits of a first of the q-bit operands being respectively supplied to the first selection inputs, and the bits of the second q-bit operand being respectively supplied to the second selection inputs.

A method and a device for tuning and control of industrial processes having varying material flow rate. An adder is configured to add excitation signals to the controller output signal. A measurement system is configured to measure a property in response to the excitation signals. A model based tuning unit is adapted to estimate the value of at least one parameter with unknown value of a process model structure describing the effect of varying material flow rate, based on the measurements of the property and the output signal from the controller, and to calculate a model that describes the dynamics from controller output to controller input based on the estimated value of the parameter, and to perform model based tuning of the controller based on the model that describes the dynamics from controller output to controller input.

More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one.. The NSRF value is calculated as equaling (ZWLM slack value +negative slack value) / ZWLM slack value=(1+(negative slack value / ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.

A chopper-direct-conversion (CDC) radio receiver includes a phase-alternating mixer receiving an antenna input signal and at least one local oscillator signal and generating a double sideband signal in a single mixing step. The phase-alternating mixer may be implemented by two parallel mixers each mixing the input signal with one of two local oscillator signals and an adder receiving and summing outputs from the two parallel mixers, by a track-and-hold circuit sampling the input signal based upon the local oscillator signal, or by a window averaging circuit averaging the input signal across a period of the local oscillator signal. The CDC architecture is suitable for fabrication on a single chip and offers solutions to virtually all problems found in conventional direct-conversion receivers.

This invention relates to a method for automatically configuring address in MANET which combines itself with AODV route to increase repeated address test efficiency including: first of all, the s, a node of MANET, generates a temporary address for transmitting address configuration information and generates an experiment address then to broadcast AREQ and test the uniqueness of the requested address. The nodes who got the AREQ should refresh the route lists, if MANET node finds its own IP address or that in the route list is the same with the adder, that shows the adder is used. AREP is broadcast to s which generates a new address after receiving AREP and repeats the adder test. If s does not receive AREP, it assigns the adder to netcards.