124 results about "Baseline wander" patented technology

An embodiment of the proposed invention is primarily applied to compensate the BLW in communication systems using THPs in their transmitters, especially suitable for the 10GBase-T Ethernet application. The present apparatus includes an additional decision device (slicer) used to generate DC offset information (error signal) and an extra modulus unit after our BLW compensator to reconvert compensated symbols to correct 16-PAM signals. In addition, the estimated error signals in our method are generated from the difference between the input of the BLW compensator and the output of the decision device. These error signals are then weighted to alleviate the impact of erroneous DC offset information on the performance of the BLW compensator. Therefore, a more direct and accurate DC offset information can be derived to improve the inaccurate BLW estimation in previous works.

In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

An embodiment of the proposed invention is primarily applied to compensate the BLW in communication systems using THPs in their transmitters, especially suitable for the 10GBase-T Ethernet application. The present apparatus includes an additional decision device (slicer) used to generate DC offset information (error signal) and an extra modulus unit after our BLW compensator to reconvert compensated symbols to correct 16-PAM signals. In addition, the estimated error signals in our method are generated from the difference between the input of the BLW compensator and the output of the decision device. These error signals are then weighted to alleviate the impact of erroneous DC offset information on the performance of the BLW compensator. Therefore, a more direct and accurate DC offset information can be derived to improve the inaccurate BLW estimation in previous works.

A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. Baseline wander of the signal is corrected sequentially by each of the plurality of baseline wander correcting units. At least a baseline wander correcting unit placed in the initial stage may correct baseline wander by a feedback control. The baseline wander correcting units correct the baseline wanders, respectively, so that the wander of baseline can be efficiently corrected.

An AC coupled receiver incorporates a decision feedback restore technique that is readily implemented on a monolithic integrated circuit to reduce or eliminate effects of baseline wander in a non-return-to-zero (NRZ) data receiver. In at least one embodiment of the invention, a method includes at least substantially attenuating at least a DC portion of a received signal to generate a first signal. The method includes generating a low frequency signal based at least in part on a reference signal selected from a plurality of reference signals. The method includes generating a restored signal based at least in part on the first signal and the low frequency signal.

Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the transformer model is used estimate and cancel the baseline wander effect. A parametric model is used to model the baseline wander impairment created by the transmitter and receiver transformers as a high pass filter having an exponential decay parameter alpha. A correction signal for both the far end and echo signal paths are calculated and summed to generate a total correction signal. The total correction signal is partitioned into an analog correction signal that is applied to the analog portion of the communications receiver and into a digital correction signal that is similarly applied to the analog portion of the communications receiver.

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.