124 results about "Baseline wander" patented technology

A baseline wander correcting unit is provided in a processing path in which a predetermined processing is performed on an input signal. The baseline wander correcting unit includes a baseline wander derivation unit which derives an amount of wander of baseline of a signal on which the predetermined processing has been performed, and an adjustment unit which adjusts an amount of wander of the baseline derived by the baseline wander derivation unit and outputs a baseline correction amount, so that the baseline wander correcting unit corrects the baseline wander by a feedforward control. The correction by the feedforward control ensures the baseline wander in the event of an instantaneous wander.

An embodiment of the proposed invention is primarily applied to compensate the BLW in communication systems using THPs in their transmitters, especially suitable for the 10GBase-T Ethernet application. The present apparatus includes an additional decision device (slicer) used to generate DC offset information (error signal) and an extra modulus unit after our BLW compensator to reconvert compensated symbols to correct 16-PAM signals. In addition, the estimated error signals in our method are generated from the difference between the input of the BLW compensator and the output of the decision device. These error signals are then weighted to alleviate the impact of erroneous DC offset information on the performance of the BLW compensator. Therefore, a more direct and accurate DC offset information can be derived to improve the inaccurate BLW estimation in previous works.

A circuit for correcting baseline wander in a transmitter which includes a main signal current driver driving a first winding of a two-winding transformer which first winding is in parallel with a termination impedance matching load, in which a compensation current driver is coupled in parallel with the main signal current driver for adding its current to current of the main signal current driver. A correction signal control input is provided to the compensation driver. A sample-and-hold circuit is connected across the first winding, an error amplifier having a first pair of inputs is connected across the first winding and a second pair of inputs are connected to the output of the sample and hold circuit. These provide an error signal resulting from a difference of signals appearing at its respective pairs of inputs. A circuit is provided for applying the error signal to the correction signal control input of the compensation current driver, whereby any difference between a present signal carried by the first winding of the transformer, and a past signal held by the sample-and-hold circuit, results in an error signal and generation of a correcting current by the compensation current driver so as to substantially eliminate the difference.

In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

A device and method for correcting the baseline wandering of transmitting signals are disclosed. The present method and device are used to correct the baseline wandering of the first output terminal and the second output terminal of a receiver as a result of induction effect of the transformer. The present device comprises a compensation current source including a first compensation output terminal and a second compensation output terminal which are respectively connected to the first output terminal and the second output terminal of the receiver. The device further includes a voltage signal generator for generating a control voltage to control the compensation current source. The voltage signal generator employs the voltage difference of the first output terminal and the second output terminal of the receiver and a reference voltage to control the control voltage. Thereby, the compensation current value of the compensation current source is supplied to the first output terminal and the second output terminal of the receiver and is used to correct the baseline wandering.

A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the transformer model is used estimate and cancel the baseline wander effect. A parametric model is used to model the baseline wander impairment created by the transmitter and receiver transformers as a high pass filter having an exponential decay parameter alpha. A correction signal for both the far end and echo signal paths are calculated and summed to generate a total correction signal. The total correction signal is partitioned into an analog correction signal that is applied to the analog portion of the communications receiver and into a digital correction signal that is similarly applied to the analog portion of the communications receiver.

A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount. The fine correcting by the first baseline wander correcting unit and the coarse correcting by the second baseline correcting unit ensure efficient correction of baseline wander.

An AC coupled receiver incorporates a decision feedback restore technique that is readily implemented on a monolithic integrated circuit to reduce or eliminate effects of baseline wander in a non-return-to-zero (NRZ) data receiver. In at least one embodiment of the invention, a method includes at least substantially attenuating at least a DC portion of a received signal to generate a first signal. The method includes generating a low frequency signal based at least in part on a reference signal selected from a plurality of reference signals. The method includes generating a restored signal based at least in part on the first signal and the low frequency signal.

A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.

The invention discloses a method for generating a judge index for electrocardio interference signal recognition, comprising A1. acquiring an electrocardio signal to obtain an electrocardio signal data sequence; B1. grouping the data sequence in certain time period and counting the minimum value in each group; D1. looking up the minimum value and the maximum value in the minimum value set composed of looked-up minimum values in each group; E1. recognizing the low-frequency interference and the irregular interference by the difference of the maximum value and the minimum value looked up in the step D1 as a first baseline drift judge index. The invention detects existing noise based on objective, and generates a reasonable judge index based on the existing noise, so that the interference can be effectively recognized, thereby improving the reliability of electrocardio signal analysis result.

The invention discloses an electrocardiogram baseline drifting correction method based on robust estimation and a plurality of intrinsic mode functions, belonging to the technical field of electrocardiosignal processing. Original electrocardiosignals to be treated are extended, then MEM filtration is carried out, filtration results are used as preliminary estimation BWe of the baseline drifting, the EMD (empirical mode decomposition) is carried for the filtration results to obtain a group of intrinsic mode functions IMF, and the IMF is screened based on testing with t; summation reconstruction is carried out for the selected IMF, and reconstructed results are deducted from the BWe obtained in the third step to obtain estimated baseline drifting signals BW; and then the BW is deducted from the original electrocardiosignals to obtain signals after correction. The supremum estimation of baseline drifting information is carried out via the MEM, more reasonable baseline drifting information can be obtained via EMD decomposition and correction, and thus high-quality electrocardiosignals can be obtained.

A novel and useful mechanism for the mitigation of baseline wander from wired networks such as Ethernet. A high pass filter is inserted before the analog to digital converter having a pole within the range of 5-12 MHz. This eliminates the need for any other baseline wander removal schemes, whether analog or digital and provides sufficient performance in terms of noise budget.

In a perpendicular magnetic recording system, the data that is being written by the write channel is fed back into the read channel. The read channel processes the data and decides if the written sequence is likely to have very poor DC characteristics. If that is the case, the write channel changes a scrambler seed and rewrites the data using the new scrambler seed. The data may also be inspected for patterns that might cause large baseline wander before being written to disk, i.e., in the write channel. A data sequence may be repeatedly scrambled and encoded until an acceptable level of estimated DC-wander has been achieved. The data sequence may then be written to disk.

An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

The invention discloses a test substance concentration calculation method applied to a rapid test strip detection technology. The method comprises the steps as follows: detecting a standard concentration sample to fit a standard concentration curve between T / C and concentration of a target test substance, and acquiring a photograph of the test strip impregnated with the test substance; cutting out the part,containing a fluorescent signal, of the photograph; performing grayscale processing to obtain a two-dimensional array; calculating the average of all the rows (or columns) of the two-dimensional array to obtain a one-dimensional array; removing noise by filtration; eliminating baseline drift; searching for the peak and calculating the peak area ratio T / C; substituting the peak area ratio into the standard concentration curve for conversion of a concentration value. With the adoption of the method, an accurate ratio T / C of the detection band signal T to the quality control band signal C can be obtained, taken as judgment information and substituted into the standard concentration curve, and the accurate concentration of the test substance is obtained, therefore, the accuracy of detection is effectively improved.

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

A method and device for compensating for undesirable signal characteristics such as baseline wander that includes a linear equalization filter responsive to receive an input, a combiner responsive to an output of the linear equalization filter, and a decision feedback equalization filter responsive to an output of the combiner, where the combiner is further responsive to an output of the decision feedback equalizer. Additionally, an error feedback circuit is responsive to the output of the combiner, and the combiner is further responsive to an output of the error feedback circuit to form a compensated signal having reduced distortion relative to the distorted signal.

A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. Baseline wander of the signal is corrected sequentially by each of the plurality of baseline wander correcting units. At least a baseline wander correcting unit placed in the initial stage may correct baseline wander by a feedback control. The baseline wander correcting units correct the baseline wanders, respectively, so that the wander of baseline can be efficiently corrected.

Abstract of Disclosure A method for compensating a baseline wander of a transmission signal and related circuit are provided. The transmission signal includes a plurality of first pulses and a plurality of second pulses for representing digital data coded in the transmission signal. The method includes generating an accumulation result according to a number of the first pulses and a number of the second pulses for estimating the baseline wander of the transmission signal, and compensating the baseline wander of the transmission line according to the accumulation result.

The invention discloses a baseline drift voltage correcting circuit used for an internet access chip. The baseline drift voltage correcting circuit comprises a common-mode adjusting module, a comparer module, a digital processing module, a charge pump module, a voltage-controlled current source module and a baseline drift correcting module. Input differential signals after passing through the common-mode adjusting module are adjusted to be within an input range of a comparer; the comparer compares the differential signals at a positive end and a negative end and outputs square waves; the digital processing module controls the charge pump module to output different control voltages based on the duty ratio of the square waves output by the comparer; and the control voltages control the volume of compensating current in a baseline drift module so as to finish correction for the baseline drift of the input signals. The baseline drift voltage correcting circuit determines and compensates signal DC and low-frequency attenuation caused by a high-pass characteristic of an isolation transformer, corrects the baseline drift in the signal transmission and improves the noise margin of the circuit. Meanwhile, the design difficulty of a simulation circuit is reduced, the dynamic input range of an ADC is no longer sacrificed, and the baseline drift voltage correction range of the circuit is enlarged.

The invention discloses a wave filter merging method applied to a self organization pulse sensor. The method obtains multi-path pulse wave curves through placing a plurality of piezoelectric sensor point lattices at radial artery parts on the inner side of the wrist, wherein each single-point sensor can separately measure the pulse wave. The curves carry out digital wave filtering and factor analysis in an information merging center according to the following steps that: firstly, the digital wave filtering adopts a small wave processing method, and noise signals such as base line drifting, electromyographical interference, power frequency interference and the like mixed in the pulse waves can be effectively eliminated; and then, the multi-path pulse signals after the wave filtering carry out dimensionality reduction processing through the factor analysis, signal channels with server distortion in the multi-path pulse signals are eliminated, at the same time, two paths of pulse signals are optimized and selected, and finally, the two paths of pulse signals are merged into one path of pulse signals to be output. When the method of the invention is adopted, the real-time output weighing regulation of the sensor point lattices can be realized, so a path of pulse signals nearest to the actual pulse signals can be obtained, and then, the monitoring and the analysis of the real-time pulse signals can be finally realized through the connection of a wireless communication module and a subsequent processing module.