5460 results about "Charge pump" patented technology

A station having a means for receipt of ambient energy from the environment and energizing power storage devices of objects of interest comprising one or more antennae and circuitry for converting said ambient energy into DC power for energizing said power storage devices. The circuitry for converting the ambient energy into DC power may include a rectifier / charge pump. The antenna of the station is tuned to maximize DC energy at the output of the rectifier / charge pump. The station can be used to energize power storage devices including capacitors and batteries that are used in electronic devices, such as cell phones, cameras, PDAs. Various antenna constructions may be employed.

A DC / DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC / DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios.

A power control circuit is provided containing a switch array, which includes segmented switches, a flying capacitor, an output voltage terminal, a feedback loop, and a digital voltage regulator block. The digital voltage regulator block includes an A / D converter, an encoder, an add-subtractor, and a gate logic. These power control circuits do not include pass transistors. A method is also provided, where the charge pumps of the power control circuit are operated in two-phase cycles including a charging phase and a pumping phase. The power control circuit is controlled in both of these phases, thereby reducing the ripple of the output voltage.

A novel RF buffer circuit adapted for use with an RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

In a Dickson type charge pump in which a plurality of serially connected diodes sequentially respond to anti-phase 50 / 50 clock cross over or overlapped (φ1, φ2), efficiency of the charge pump is increased by providing with each diode a charge transfer transistor in parallel therewith between two adjacent nodes, and driving the charge transfer transistor to conduction during a time when the parallel diode is conducting thereby transferring any residual trapped charge at one node through the charge transfer transistor to the next node. Operating frequency can be increased by providing a pre-charge diode coupling an input node to the gate of the charge transfer transistor to facilitate conductance of the charge transfer transistor, and by coupling the control terminal of the charge transfer transistor to an input node in response to charge on an output node to thereby equalize charge on the control terminal and on the input node during a recovery period.

A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.

A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

A PLL circuit and a DLL circuit able to stabilize a control voltage within a short time after a phase pull-in operation in each cycle of a reference clock. In a phase comparator, the size of a leading phase or a delayed phase of a feedback signal is detected with respect to a reference clock signa, and pulse signals having pulse widths corresponding to the size are output. A current corresponding to the signals is output from a charge pump circuit to a lag-lead filter, and a control voltage obtained by removing noise of the above output is output from a low-pass filter to a voltage-controlled oscillator. Furthermore, through capacitors, pulse signals are superposed on the control voltage, and a sharp waveform is obtained by correcting blunting of the waveform by the low-pass filter. Due to this, the control voltage is stabilized within a short time after a phase pull-in operation in each cycle of the reference clock signal.