238 results about "Voltage doubler" patented technology

This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a unidirectional switch, a voltage multiplier, and a current limiter. In some cases, these components can be a diode, voltage doubler, and an inductor, respectively.

A half-bridge inverter is used for a high frequency alternating current power supply to be connected to a primary side of a contactless power transformer, and a voltage-doubler rectifier is used to convert a secondary-side alternating current output of the contactless power transformer into a direct current.

A multi stage voltage pumping circuit includes a plurality of voltage pumping stages each operated by a first clock signal and a second clock signal for raising a voltage level of an inputted voltage; and a plurality of charge storing means each connected to outputs of the plurality of voltage pumping stages respectively except for a last voltage pumping stage in order to store charge, wherein each of the plurality of voltage pumping stages is a cross coupled voltage doubler and an output of a previous voltage pumping stage is connected to an input of a next voltage pumping stage.

A two-inductor boost converter includes an integrated magnetic core having a three-legged flux-conducting element with an energy-storing gap, for example in the center leg. Two primary windings are disposed on respective legs, such as the outer legs, and are coupled in parallel to one input terminal of the converter. Two series-connected secondary windings are also disposed on the flux-conducting element, and are connected to rectification and filtering circuitry which may have full bridge, full wave, or voltage doubler configuration. Primary-side switches are coupled in series between each primary winding and the other converter input terminal. Control circuitry generates control signals for the primary-side switches, providing for a desired degree of overlapped conduction during each operating cycle along with periods of non-conduction that result in transferring electrical energy to the load. The integrated magnetic core can include additional windings for ancillary functions, such as for flyback operation during start-up.

A multi-level rectifier is presented that is suitable for use at high frequencies, including into MHz range such as in the 6.78 MHz band used for wireless power transfer. Depending on the amplitude of the input waveform, the rectifier can be operated in different modes. For lower input levels, the rectifier acts as a voltage doubler. For higher input levels, the impedance of the rectifier can be varied based on the input level. The rectifier is a synchronous rectifier with a front section and a back section, where the impedance is varied by changing the phase of the control signal of the back section relative to that of the front section.

A driver circuit provides a driving signal to the power stage of a switched mode power supply in correspondence with a pulse width modulated duty cycle. A voltage doubler circuit including a bucket capacitor and plural switches is arranged to successively couple the bucket capacitor to the input power source and to the driver circuit. The voltage doubler circuit thereby provides the driving signal to the driver circuit having a voltage approximately double the corresponding voltage of the input power source. The voltage doubler circuit discharges the bucket capacitor into the driver circuit to provide the driving signal in correspondence with a first portion of the pulse width modulated duty cycle, and the voltage doubler circuit recharges the bucket capacitor in correspondence with a second portion of the pulse width modulated duty cycle. The power switch comprises an internal capacitance, wherein charge stored in the bucket capacitor is transferred to the internal capacitance of the at least one power switch during the first portion of the pulse width modulated duty cycle. Remaining charge in the internal capacitance of the power switch is recycled back to the bucket capacitor during the second portion of the pulse width modulated duty cycle.

A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention. Accordingly, the present invention includes control schemes to field program basic circuit element or any critical nets, and to alter the functionality of certain predetermined circuit units, and update array interconnections, accessing stored protocols, algorithms in all chips in the embodiment subsystem of a SFPGA chip sets.

A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.

The present invention constitutes a control circuit which permits the dimming of the illumination emitted from a fluorescent lamp. A controllable source of alternating current power is converted to direct current utilizing a conventional diode bridge and power filter. The direct current signal is converted to a high frequency alternating current signal using a self-oscillating inverter circuit. The output of the inverter circuit is coupled to a resonance circuit. The lamp will be turned on when the output of the resonance circuit is increased until it exceeds the minimum voltage specified for the selected fluorescent lamp. A voltage doubler circuit powers the fluorescent lamp and permits the fluorescent lamp to be dimmed or otherwise remain illuminated when the input alternating power is reduced below that specified for normal operation of the fluorescent lamp.

A power supply circuit for a dimmer switching device includes a voltage doubler circuit, a filter circuit, a switching power supply, and a linear regulator circuit. In one embodiment, the voltage doubler circuit includes a first stage having a first capacitor and a first diode, and a second stage having a second capacitor and a second diode. The switching power supply may include a feedback circuit, and may be a non-isolated power supply. In an embodiment, the dimmer device is variable between an OFF position and a full ON position, and the circuit is effective to provide power for operation of the switching power supply while the dimmer device is in the full ON position.

An envelope detector circuit, suitable for use in RFID tags, includes a voltage doubler circuit and a biasing voltage generating circuit which comprises components matched respectively to rectifying components of the voltage doubler circuit. A rectifying component of this voltage doubler circuit is formed by a transistor controlled by the biasing voltage generating circuit which provides a biasing voltage to a control gate of this transistor, the biasing voltage generating circuit being arranged so as to permit a determined forward biasing current to flow through the transistor and further rectifying elements of the voltage doubler circuit. This embodiment provides fast, highly sensitive detection of envelope waveforms in input signals. Thanks to the matched rectifying components, efficiency variations due to variations in manufacturing process can be eliminated. The envelope detector circuit is further arranged for maintaining a stable detection independent of variations in temperature.

A system to control an asynchronous tri-phase motor where said system comprises: at least one filter directly coupled to the current of the Alternative Current (AC) line; a rectifier which rectifies the line current, a doubler which reduces the curl, elevates the voltage and delivers a voltage in Direct Current, a braking resistance which helps to dissipate energy when the system is in braking mode, a shunt resistance, which helps to measure the current which flows from the V-line between the doubler and the IGBT module, a source, which adapts the voltage which the microcontroller consumes and peripheries (operational amplifiers, detectors, etc.), a line regulator to remove curls and line noise, a microcontroller to process, admit and emit control signals, a potential module which emits a PWM train pulse with a frequency determined by the microcontroller towards the IGBT module when the microcontroller indicates such, an IGBT module, which receives the PWM pulse train adapting and coupling them to an H bridge, to thus allow the flow of high voltage in DC emanating from the doubler towards the electric motor, a retro-feeding line towards the microcontroller to measure current, a velocity detector coupled mechanically to the motor and which sends a signal or pulse train towards the microcontroller; as well as the acceleration or braking methods consistent in the measurement of the slip S of said tri-phase motor.