1107results about How to "Reduce circuit size" patented technology

A drive circuit which outputs an output signal to an output terminal, includes a drive transistor configured to output a gradation current to the output terminal; a single differential amplifier; a resistance element connected with the drive transistor; and a plurality of switches. The plurality of switches are controlled such that a precharge voltage is outputted from the differential amplifier to the output terminal in a first period while blocking off an output from the drive transistor and such that a gradation current is outputted from the drive transistor to the output terminal in a second period after the first period.

A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.

The present invention provides a high frequency power amplifier of an open-loop type, which outputs a signal having a level corresponding to an output level required under control of a power supply voltage for each output power FET, based on a control signal for the output level. The high frequency power amplifier is provided with a bias voltage generating circuit which generates a gate bias voltage of each output power FET according to an output voltage of a power control circuit for controlling the power supply voltage for the output power FET, based on the control signal for the output level.

The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

A display device is provided with a display panel; a backlight which illuminates the display panel; and a backlight brightness controller controlling a brightness of the backlight so that the brightness of the brightness is variable in the middle of each frame period.

To implement a solid-state image pickup element in which the peripheral circuit is downsized, there is provided a solid-state image pickup element including a plurality of pixel blocks each having a plurality of photoelectric conversion elements, a plurality of transfer switches each having one terminal connected to a corresponding photoelectric conversion element, a signal input portion commonly connected to the other terminal of each of the plurality of transfer switches, and an amplifier connected to the signal input portion, and a scanning circuit for outputting a scanning clock for each pixel block.

The invention achieves a visual processing device that can execute precise contrast adjustment on image signals that have been input and that does not cause discrepancies in the output timing of the image signals that are output. The visual processing device is provided with a gain-type visual processing portion that outputs a first gain signal having predetermined gain characteristics with respect to the input image signal, and a correction portion that corrects the input image signal based on the first gain signal.

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

Provided is an information processing apparatus which includes a first-module including a first narrow-band communicator for performing narrow band communication with a second-module, a first broadband-communicator for performing broadband communication with the second-module, and a first controller for controlling an operation state of the first broadband-communicator according to an operation mode, and a second-module including a second narrow-band communicator for performing narrow-band communication with the first-module, a second broadband-communicator for performing broadband communication with the first-module, and a second controller for controlling an operation state of the second broadband-communicator according to an operation mode. The first controller places the first broadband-communicator in an operation state in a first mode, and places the first broadband-communicator in a standby state in a second mode. The second controller places the second broadband-communicator in an operation state in the first mode, and places the second broadband-communicator in a standby state in the second mode.

In a driving device (20) for driving an IGBT (1), a current measuring portion (22) measures a main current amount flowing through the IGBT (1). When the main current amount measured by the current measuring portion (22) reaches a predetermined reference level, a protection circuit portion (23) limits the main current at the IGBT (1) to protect it. A temperature measuring portion (24) measures the temperature of the IGBT (1). The control portion (25) adjusts the aforementioned reference level based on the temperature of the IGBT (1) measured by the temperature measuring portion (24). A control portion (35) stores setting values of the reference level as data.

A switching power supply circuit in which a series circuit comprising a resistive element and a capacitive element is provided in a parallel configuration with an inductor which supplies a load current to a load circuit, a voltage comparator having first and second threshold voltages discriminates a voltage obtained from a mutual connecting point of the series circuit therefrom and controls a switch element for supplying a current to the inductor, thereby varying the current supplied to the inductor in accordance with a variation in the load current is combined with a series power supply circuit which shares the load current of the load circuit.

A wireless communication system is disclosed. The wireless communication system performs data transmission using spatially multiplexed streams from a first terminal including N antennas to a second terminal including M antennas (N and M are integers larger than or equal to 2 and N>H).

A conventional charge pump circuit requires a step-up circuit or the like for turning on or off a transistor. Therefore, it has a problem of an increase in circuit scale, which leads to increases in circuit area and power consumption. One feature is to provide a charge pump circuit including a first transistor, a switch, a first capacitor, a second capacitor, and an inverter, in which one electrode of the first transistor is connected to a first potential, an output side of the inverter is connected to the other electrode of the first transistor and one side of the switch through the first capacitor, the other side of the switch is connected to a second potential through the second capacitor.

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

A wireless communication system is disclosed. The system performs data transmission from a first terminal including N antennas to a second terminal including M antennas using spatially multiplexed streams (N and M are integers larger than or equal to 2).

A data discriminating unit includes a data discriminator and a sync signal discriminator. A data sync signal is detected for the bit string discriminated from the output of the sync signal discriminator, and the data is demodulated for the bit string discriminated from the output of the data discriminator, thereby optimizing the signal to a form suitable for discrimination and detection of the data sync signal and demodulation for data reproduction. As a result, the detection performance of the data sync signal can be improved while maintaining the data discrimination performance. A Viterbi decoder is used for discrimination by the data discriminator and the sync signal discriminator for the optimization thereby to optimize the number of states, the number of paths for state transition and the path memory length. A signal having no continuous inversions of the recording data is used as the data sync signal.