1620 results about "Reference level" patented technology

A method and system for detecting whether an antenna is property connected to a distributed antenna network. The current drawn by the antenna is measured and compared against an expected current draw or reference level. The measured level of current drawn by the antenna is indicative of whether the antenna is properly connected or is disconnected. The comparison results may be used as the basis for creating a status message, which is then communicated to a central monitoring unit for each antenna. The central monitoring unit may generate appropriate alarms in response to a status message indicating a fault condition at a particular antenna.

Exemplary embodiments provide a system, method and apparatus for regulating current in loads, such as in an array of independent pluralities of light emitting diodes (“LEDs”). An exemplary system comprises a multiplexer adapted to switch current to each independent string of LEDs; a first controller to maintain a substantially constant average current level to the plurality of LEDs; and a second controller to modulate a current amplitude and duration of time division multiplexing for each independent string of LEDs. Another aspect of the system provides for modulating the on time for switching current to maintain a substantially constant average current level and to respond and converge quickly to changing current reference levels.

Provided is a detector system for detecting a plurality of items each having at least one RFID tag attached thereto. The detector system may include a presence detector and / or a message detector. The presence detector may include a signal reader which receives modulated carrier frequencies from the RFID tags during a predetermined response time period for comparison to a reference level. The signal reader may be configured as a power integrator or a constellation discriminator. The power integrator sums the power contained in signals transmitted by the RFID tags by integration for comparison to an environmental noise level measurement taken during a quiet period. For the constellation discriminator, bits contained in the modulating message are compared to the bit pattern of a predetermined reference constellation. The detector system may be configured as a 3-state detector which combines the presence detector with a message detector that indicates the identification code of the RFID tags.

The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and / or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is erased. If a memory cell has a current less than a first sense amplifier current reference level, additional erase pulses are applied to that cell until either the erase current is in the range of 30–40 μA or a maximum quantity of erase pulses have been applied. A leakage check is performed to determine if any cells have been overerased. If a cell has an erase current greater than or equal to a second sense amplifier current reference level, soft programming pulses are applied to the cell until either its erase current is less than the second reference level or a maximum quantity of soft program pulses have been applied.

The invention relates to a method and an electronic device for implementing the method for measuring mental load. The electronic device generates at least two different cognitively loading tasks for the person participating in the measurement, the first task determining a reference level and at least one other task determining the loading capacity level. The electronic device determines the pulse parameters of the person participating in the measurement during the cognitively loading tasks. The electronic device also compares the pulse parameters during the different tasks with each other. Finally, the electronic device generates a value descriptive of the mental load of the person participating in the measurement on the basis of the comparison of the pulse parameters.

A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (123), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).

A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.