Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

3951results about How to "Increase current" patented technology

Thin film transitor substrate and method of manufacturing the same

InactiveUS20080258143A1Increases process time and leakage current and serial contact resistanceDegrading property of TFTTransistorSemiconductor/solid-state device manufacturingOxide semiconductorOxide
A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.
Owner:SAMSUNG ELECTRONICS CO LTD

Semiconductor integrated circuit device

A DRAM capacitor uses ruthenium or ruthenium oxide as an upper electrode and hafnium dioxide or zirconium oxide as an insulation layer. The DRAM capacitor is intended to suppress diffusion of ruthenium, etc. into hafnium dioxide. Tantalum pentoxide or niobium oxide having a higher permittivity than that of the insulation layer is inserted as a cap insulation layer to the boundary between the upper electrode of ruthenium or ruthenium oxide and the insulation layer of hafnium dioxide or zirconium oxide to thereby suppress diffusion of ruthenium, etc. into hafnium dioxide, etc.
Owner:HITACHI LTD

Calendar-enhanced awareness for instant messaging systems and electronic status boards

A method, system, and product are disclosed for providing calendar-enhanced awareness / presence information for instant messaging systems and electronic status boards. This invention automates status transitions, enhances and automates status messages, and automates and extends the IM “who can see me” function. Additionally, this invention extends awareness to dimensions other than IM status, to include availability in-person, via telephone, via wireless device or wireless messaging device (e.g., pager).
Owner:IBM CORP

Energy transfer amplification for intrabody devices

InactiveUS20050027192A1Improved power transferImprove wireless transferSurgeryJoint implantsPower circuitsEngineering
Apparatus for driving current in a power circuit of a medical device inserted into a body of a subject includes a power transmitter, which is adapted to generate, in a vicinity of the body, an electromagnetic field having a predetermined frequency capable of inductively driving the current in the power circuit. A passive energy transfer amplifier, having a resonant response at the frequency of the electromagnetic field is placed in proximity to the medical device so as to enhance the current driven in the power circuit by the electromagnetic field.
Owner:BIOSENSE WEBSTER INC

METHOD OF MANUFACTURING ZnO SEMICONDUCTOR LAYER FOR ELECTRONIC DEVICE AND THIN FILM TRANSISTOR INCLUDING THE ZnO SEMICONDUCTOR LAYER

Provided are a method of manufacturing a ZnO semiconductor layer for an electronic device, which can control the size of crystals of the ZnO semiconductor layer and the number of carriers using a surface chemical reaction between precursors, and a thin film transistor (TFT) including the ZnO semiconductor layer. The method includes: (a) loading a substrate into a chamber; (b) injecting a Zn precursor into the chamber to adsorb the Zn precursor on the substrate; (c) injecting an inert gas or N2 gas into the chamber to remove the remaining Zn precursor; (d) injecting an oxygen precursor into the chamber to cause a reaction between the oxygen precursor and the Zn precursor adsorbed on the substrate to form the ZnO semiconductor layer; (e) injecting the N2 gas or inert gas into the chamber to remove the remaining oxygen precursor; (f) repeating steps (a) through (e); (g) repeatedly processing the surface treatment of the ZnO semiconductor layer using O2 plasma or O3; (h) injecting the N2 gas or inert gas into the chamber to remove the remaining oxygen and Zn precursors; and (i) repeating steps (a) through (h) to control the thickness of the ZnO semiconductor layer. In this method, a transparent TFT is formed using a transparent substrate to enable manufacture of a transparent display device, and a flexible display device can be manufactured using a flexible substrate. Also, the crystallinity of the ZnO semiconductor layer can be increased to improve the mobility of a TFT, and the number of carriers can be controlled to reduce a leakage current. Therefore, a ZnO semiconductor having excellent characteristics can be manufactured.
Owner:ELECTRONICS & TELECOMM RES INST

Strained silicon finFET device

Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.
Owner:MICROSOFT TECH LICENSING LLC +1

Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories

A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.
Owner:PROMOS TECH INC

Systems and methods for electrosurgical tissue contraction

InactiveUS7094215B2Limiting thermal damage and dissociationSuppress thermal damageEye treatmentSurgical instruments for heatingSacroiliac jointSurgical department
Systems and methods are provided for performing electrosurgical interventions, such as selectively contracting soft collagen tissue and other body structures, while limiting thermal damage or molecular dissociation of such tissue and limiting the thermal damage to tissue adjacent to and underlying the treatment site. The systems and methods of the present invention are particularly useful for surgical procedures in electrically conducting environments, such as arthroscopic procedures in the joints, e.g., shoulder, knee, hip, hand, foot, elbow or the like. The present invention is also useful in relatively dry environments, such as treating and shaping the cornea, and dermatological procedures involving surface tissue contraction of tissue underlying the surface of the skin for tissue rejuvenation, wrinkle removal and the like.
Owner:ARTHROCARE
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products