178results about How to "High-speed switching" patented technology

Disclosed herein is a SONET / SDH transmitter provided in a transmission system in which a SONET / SDH network and an IP network are connected with optical LAN-IF. The SONET / SDH transmitter has a redundancy transmission line structure consisting of two transmission lines, a K-packet processing section, and a transmitting section. The K-packet processing section is used for generating a specific byte (SONET K1 / K2 byte) of data representing transmission-line switching control information about the transmission lines, packetizing the generated data, and outputting a packet. The transmitting section is used for transmitting the packet to the transmitter provided opposite through the transmission lines. This SONET / SDH transmitter further has a redundancy line switching section. The redundancy line switching section is capable of selecting a transmission line, where a transmission signal with information data is transmitted, according to a status in which a packetized specific byte of data from the transmitter opposite is received.

A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.

An optical semiconductor device has a structure in which a semiconductor active layer is sandwiched by a p-type semiconductor cladding layer and an n-type semiconductor cladding layer and a p-type contact layer is formed on the p-type semiconductor cladding layer side and an n-type contact layer is formed on the n-type semiconductor cladding layer side, wherein two ferromagnetic layers are formed on the n-type contact layer and two ferromagnetic layers are formed on the p-type contact layer. Magnetization directions of a pair of ferromagnetic layers vertically opposed to each other are set to be parallel to each other, and the magnetization directions of adjacent ferromagnetic layers are inverted to each other.

A relay gateway apparatus HO-GW is provided between heterogeneous access networks (a WiMAX access network and a UMB access network). The HO-GW performs conversion of a movement control signal (an Inter-AGW handover control signal) and relay of communication data. When the relay is performed, user data from a CN reaches a wireless terminal MN through an HA of a core network, an access router ASN-GW, the HO-GW, and a base station eBS.

Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that can serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 μm, preferably greater than 3 μm, more preferably greater than or equal to 10 μm, and end portions of one of electrodes that are in contact with the oxide semiconductor is placed inside end portions of the oxide semiconductor.

The invention reveals an IOV (Internet of vehicles) system based on an OTA protocol, and a control method therefor. The control method comprises the following steps that a server achieves the notification of vehicle-mounted terminal equipment; the vehicle-mounted terminal equipment transmits a safe connection request to the server, and enables the information of vehicle-mounted terminal equipment to be transmitted to the server, so that the server carries out identity verification; the server transmits a remote instruction to the vehicle-mounted terminal equipment; the vehicle-mounted terminal equipment executes the instruction; the vehicle-mounted terminal equipment reports the result after execution; and the server returns a confirmation result to the vehicle-mounted terminal equipment. The system and method can improve the safety and efficiency of data access, and can meet the parallel calculation demands for the safety access and parallel access of million-level vehicle-mounted terminals. The system and method can enable the vehicle-mounted terminals to be accessed safely, achieve high-speed exchange, and can achieve flexible customization and function extension.

The invention discloses a global satellite navigation system multimode radio frequency receiving method and apparatus for military and civil use, pertaining to the radio frequency communication technique field. The method provides a frequency programming in which the different narrowband signals are as mutual mirror-images of a mirror-image inhibition receiver, according to the civil narrowband signals passing through the mirror-image inhibition receiver, under the control of a time division multiplexing control system, the local oscillation frequency input from a frequency synthesizer to a radio-frequency frequency mixer and baseband frequency mixer can be periodically switched, thereby realizing the multimode paralleling receiving of the narrowband signals; while the broad band signals pass through a direct lower frequency conversion receiver, selecting a local oscillation frequency of the radio-frequency frequency mixer identical to the center frequency of the wideband GNSS, thereby realizing the receiving of each wideband mode signal for military use; the apparatus includes a mirror-image inhibition receiver and a direct lower frequency conversion receiver. The invention implementing compatibility and coordinating performance for military and civil use, and also can close the military or civil passage way for implementing the low-power consumption application requirement.

A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.

A memory device, which includes a memory layer having quantum dots uniformly dispersed in organic material disposed between an upper electrode layer and a lower electrode layer. The memory device is advantageous because it is nonvolatile and inexpensive, and realizes high integration and high speed switching. Further, size and distribution of the quantum dots may be uniform, thus realizing uniform memory behavior. Furthermore, the memory device is suitable for application to portable electronic devices that must have low power consumption, due to low operating voltages thereof.

The invention discloses a low-loss four-port non-blocking optics router based on micro-ring resonators. Through six cross waveguide micro-ring resonators and a parallel waveguide micro-ring resonator, an input end of a first port is coupled to an output end of a fourth port. An input end of a second port is coupled to an output end of the first port. An input end of the fourth port is coupled to an output end of a third port. The input end of the first port is coupled to the output end of the third port. An input end of the third port is coupled to an output end of the second port. The input end of the second port is coupled to the output end of the fourth port. A seventh micro-ring resonator is used for being connected with an optical channel from the fourth port to the first port and an optical channel from the second port to the third port. Due to the fact that the number of the micro-ring resonators is reduced to seven, the low-loss four-port non-blocking optics router based on the micro-ring resonators has the advantages of improving utilization efficiency of devices, simplifying the structure of a switch, decreasing area of the switch, reducing insertion loss and crosstalk of the switch due to the fact that the number of the cross waveguide micro-ring resonators is reduced to six, enhancing extendibility of the devices, being prone to establishing an on-chip optical interconnection network architecture and achieving high-speed transmission and exchange of optical signals.

As apparatuses which construct a ring network, a structure including a monitoring apparatus and other relay apparatuses is employed. The monitoring apparatus monitors only a ring status of such a ring network to which the own monitoring apparatus belongs. The monitoring apparatus periodically transmits health check frames from ring ports thereof respectively so as to monitor whether or not the transmitted health check frame has been received by the ring port located opposite thereto. Also, in a structure of a multi-ring network having a shared link, auxiliary health check frames are periodically transmitted from two sets of shared apparatuses respectively with respect to a monitoring apparatus of a shared link non-monitored ring network. The monitoring apparatus also monitors the auxiliary health check frames in combination with the health check frames in order to avoid an occurrence of a loop which bridges a plurality of ring networks.

The invention can achieve a recovery time that satisfies the demands of real-time transmission processing by performing, in an extremely short time period, an RSTP process in a network, which is configured in a ring topology and wherein a plurality of IEEE 802.3 compliant nodes is connected via prescribed transmission lines, using hardware to execute processes related to the physical layer and the data link layer of the OSI reference model—without software processing. The RSTP processing unit of each node: receives BPDU data, which is received from the network by one of two PHY units and stored in a BPDU send / receive buffer of a corresponding MAC unit that is connected to that PHY unit, via a BPDU data bus that is connected to that MAC unit; decodes the received BPDU data; performs a prescribed process; transfers the BPDU data, via the BPD data bus that is connected to the other MAC unit, to the other BPDU send / receive buffer; and transmits that BPDU data from the PHY unit connected to the other MAC unit to the network.

The invention provides a digital test module based on a PXI (PCI (peripheral component interconnect) eXtension for instrumentation) bus and applicable to the field of automatic test systems. The digital test module based on the PXI bus comprises a PXI bus interface circuit, a FPGA (field programmable gate array) built-in function circuit, a front drive circuit, a synchronous trigger circuit, a changeable clock control circuit and the like. A PXI module has the advantages of being high in integration level, good in board stability, high in systematical flexibility and low in cost. The PXI bus-based digital test module is an important data testing instrument; can exert digital excitation on a target system and obtain response data generated by the system according to actual requirements during the equipment debugging and the fault diagnosis of digital systems; and provides a valuable testing basis for the performance test, the field debugging and the fault diagnosis of the digital systems, thereby being wide in application range and important in application value. The development of the PXI bus-based digital test module is significant to improving the research level of digital test instruments.

To improve throughput of a substrate processing without wastefully using a source as a reactant by repeating supply steps of a plurality of reactants for a plurality of times. A substrate processing apparatus includes a source gas obtained by vaporizing a liquid source as a reactant, and functions to process a substrate by repeating the supply of the source gas into a processing chamber 1, and the supply of the reactant different from the source gas into the processing chamber 1, which is executed subsequently, for a plurality of times. A flow rate of the liquid source is controlled by an injection drive control mechanism 6. The injection drive control mechanism 6 is designed to fix the flow rate per one injecting operation of the liquid source directly flowing into a vaporization section in a vaporizer 3, and intermittently inject the liquid source to a vaporization section 31.

A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure comprising an n type first layer, a second layer containing a p type dopant laminated on the first layer, and an n type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure made of a group III nitride semiconductor, and the nitride semiconductor laminated structure formed with a first trench and a second trench, the first trench penetrating the second layer from the third layer and reaching at least the first layer, and the second trench having a side wall extending from the first, second, to third layers and being different from the first trench; a surface insulating film containing at least silicon nitride formed such that the surface insulating film covers the surface of the first trench; a gate insulating film formed on the side wall of the second trench such that the gate insulating film extends over the first, second, and third layers; and a gate electrode formed such that the gate electrode is opposed to the side wall of the second trench with the gate insulating film sandwiched between the gate electrode and the side wall.

A synthesizer that has a phase detector 8 and a charge pump circuit 9 for injecting an electric charge, or pulling it out that corresponded to a frequency difference of an input, a low-pass filter 11 for converting this electric charge into a voltage, a voltage control oscillator (VCO) 13 for changing an output frequency for this input voltage, a divider 14 for dividing the frequency of the input, and a voltage holding circuit 10 for holding the input voltage for a plurality of output frequencies of the VCO. A holding voltage of the voltage holding circuit 10 is switched with a switch 12, and the frequency of an output clock signal 3 is switched.

The invention discloses a game mode automatic on-off method comprising the steps that when the current display frame of a display equipment screen is a dynamic frame, a controlled state request signal is transmitted to external equipment via a multimedia interface; and when the received controlled contents of a controlled state response signal are non-multimedia, the current working state of the external equipment is a game operation state through judgment, and a game mode function of display equipment is powered on. The invention also discloses a game mode automatic on-off device. When the display equipment is in the dynamic frame display state, whether the external equipment connected with the multimedia interface currently works in the game operation state is judged according to the received controlled contents of the controlled state response signal, and the game mode function is powered on when the external equipment works in the game operation state through judgment so that screen resolution is reduced, frame processing speed is enhanced, frame high-speed switching is realized, and switching of the frame displayed under the game state is enabled to be more fluent.

A high-frequency switch module includes a switch IC. An impedance matching circuit is connected to the antenna port of the switch IC. The impedance matching circuit includes a high-pass filter and a low-pass filter. The high-pass filter is disposed on the side of the antenna port, and is a substantially L-shaped circuit including a capacitor and an inductor. The antenna port is connected to the ground by the inductor.

A nitride semiconductor device according to the present disclosure includes a substrate, a p-type GaN layer formed on a main surface of the substrate and made of AlxInyGa1-x-yN containing p-type impurities, where 0≦X<1, 0≦Y<1, and a Ti film formed on the p-type GaN layer. The Ti film is in a coherent or metamorphic state with respect to the p-type GaN layer.

The present invention provides a display controller and a display apparatus capable of carrying out image display in a high-speed screen switching mode without changing a data rate of a digital transmission path while a signal itself sent through a display transmission path is kept within a standard (60 Hz). A display controller 102 sequentially outputs at least two image signals, thereby allowing an image to be displayed on a liquid crystal display section 105 in accordance with the image signals, wherein among the image signals to be outputted, an image signal of a first output image and an image signal of a second output image have a relationship that provides an image having no correlation to the first output image when image brightness values of the respective signals are added for each pixel, and wherein a frame frequency when the image signal is outputted is an integral multiple of a frame frequency for an image signal of an input image, the integral multiple being two or more.

The invention discloses a method and a system for controlling a high-speed interface in a multi-processor system-on-chip, which are mainly used for solving the problems of low efficiency of receiving and sending data of the existing system. The system comprises data packet processing units, a data packet information register, a mailbox and an effective marker bit, wherein each data packet processing unit comprises multiple threads; at the data receiving end, the threads are used for directly sending out receiving requests at the speed which is close to the line speed, receiving data packets according to the receiving requests and generating data packet information; the data packet information is placed into the data packet information register, and the threads are used for keeping the sequence of the received data packets according to the data packet information in the data packet information register and working state information in the thread mailbox; and at the data sending end, the threads are used for accurately sending the data packets to corresponding ports of external equipment at high speed according to the position situation of the effective marker bit and information of a control domain. The system disclosed by the invention has the advantages of receiving and sending the data with high efficiency and reliability, and can be used for processing the network data.

The nitride semiconductor device includes: a nitride semiconductor structure comprising an n-type first layer, a p-type second layer, and an n-type third layer, the nitride semiconductor structure comprising a mesa structure having a lateral surface which forms a wall surface extending from the first, second, to third layers; a gate insulating film formed on the wall surface of the mesa structure; a gate electrode formed as facing the wall surface in the second layer; a drain electrode electrically connected to the first layer; and a source electrode electrically connected to the third layer, the nitride semiconductor structure having a high dislocation region and a low dislocation region arranged along a direction parallel to a principal surface of lamination of the nitride semiconductor structure, a dislocation density of the low dislocation region being lower than that of the high dislocation region, the mesa structure being formed in the low dislocation region.

The invention discloses a low-loss, low-crosstalk, four-port and non-blocking optical router based on micro-ring resonators. A first output optical waveguide is coupled with a first input optical waveguide through a first micro-ring resonator; the first input optical waveguide is coupled with a second output optical waveguide through a second micro-ring resonator; the second output optical waveguide is coupled with a second input optical waveguide through a third micro-ring resonator; the second input optical waveguide is coupled with the first output optical waveguide through a fourth micro-ring resonator; a first straight-through optical waveguide is coupled with the first output optical waveguide through a fifth micro-ring resonator; the first straight-through optical waveguide is coupled with the first input optical waveguide through a sixth micro-ring resonator; a second straight-through optical waveguide is coupled with the second output optical waveguide through a seventh micro-ring resonator; the second straight-through optical waveguide is coupled with the second input optical waveguide through an eighth micro-ring resonator; and the first straight-through optical waveguide is coupled with the second straight-through optical waveguide through a ninth micro-ring resonator.