Method and system for controlling high-speed interface in multi-processor system-on-chip

Abstract

The invention discloses a method and a system for controlling a high-speed interface in a multi-processor system-on-chip, which are mainly used for solving the problems of low efficiency of receiving and sending data of the existing system. The system comprises data packet processing units, a data packet information register, a mailbox and an effective marker bit, wherein each data packet processing unit comprises multiple threads; at the data receiving end, the threads are used for directly sending out receiving requests at the speed which is close to the line speed, receiving data packets according to the receiving requests and generating data packet information; the data packet information is placed into the data packet information register, and the threads are used for keeping the sequence of the received data packets according to the data packet information in the data packet information register and working state information in the thread mailbox; and at the data sending end, the threads are used for accurately sending the data packets to corresponding ports of external equipment at high speed according to the position situation of the effective marker bit and information of a control domain. The system disclosed by the invention has the advantages of receiving and sending the data with high efficiency and reliability, and can be used for processing the network data.

Description

technical field [0001] The invention belongs to the technical field of communication equipment, and particularly relates to a control method and system of a high-speed interface, which can be used for receiving and sending data in an on-chip multi-core system. Background technique [0002] System-on-a-chip can generally be divided into three parts according to functions, which are data processing part, data storage part and data exchange interface part. Whether data can enter the system-on-chip system quickly and reliably and be processed in a timely manner is directly related to the overall performance of the system, such as In a common network processor, multiple multi-threaded packet processing units, usually called PE, general-purpose main processor ARM, high-speed small-capacity static random access memory SRAM, large-capacity dynamic random access memory DRAM, data exchange interface unit constitute. Usually, the performance parameters for assessing network processors...

AI Technical Summary

Problems solved by technology

In order to solve the problem of the slow speed of a single packet processing unit, multiple packet processing units are used to work in parallel to process the data flow of a high-speed port, so that the processing capability of the packet processing unit is not limited to its maximum processing speed; active request mode When used in the process of data receiving, there is no need to poll the ready state of the port first, and the data receiving in the active request mode can work close to the line speed; it is necessary to ensure that the order of receiving incoming data is not disturbed, and at the same time, the thread can be processed in the set order. Work; To ensure that the data interface can be efficient and reliable when sending data, two effective flag positions are used to prevent the data packet processing unit and storage unit from sending data from the sending unit before all the control information and data packets are written into the sending unit. Indeterminate state caused by sending out in buffer unit

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