2195results about "Modification of read/write signals" patented technology

A magnetic sensor includes a magnetoresistance element having a peak of a thermal fluctuation strength of magnetization under a magnetic field having a certain frequency, a frequency filter connected to the magnetoresistance element and having its transmittance decreased or increased in substantially the frequency of the magnetic field to output a signal corresponding substantially to the peak of the thermal fluctuation strength of magnetization, and a detector connected to the frequency filter to detect the magnetic field based on the signal of the frequency filter.

To effectively suppress a signal in a low frequency region in which the medium noise and the signal distortion are concentrated, and in order to effectively utilize a detected component of the reproduced signal in the low frequency region, a target of partial response equalization to the perpendicularly recorded / reproduced signal is set so that the low-frequency component around the direct current is suppressed to a regulated quantity for both the effective suppression and the effective utilization. Accordingly, a maximum-likelihood decoding process is carried out through the target of partial response equalization. Reliability of data detection is made higher and a signal-to-noise ratio is improved, so that the noise from the recording medium can be reduced more and it is possible to provide a high-density magnetic recording / reproducing apparatus.

A write-once optical recording medium, and a method and apparatus for recording management information on the recording medium are provided. The method includes recording, in a temporary defect management area (TDMA), management information produced while the recording medium is in use, and transferring and recording the latest management information of the TDMA in a final defect management area (DMA) of the recording medium at a DMA fill-in stage of the recording medium.

In a disk drive that performs perpendicular magnetic recording, the read / write channel has a sync mark generator. The sync mark generator generates a second sync mark before the read / write channel operates to write data on a disk. The second sync mark has a bit pattern including a series of bits representing positive polarity and a series of bits representing negative polarity. The series of bits, which is longer than the other, has a bit length that is at least 50% but less than 85% of the total bit length of the second sync mark.

A composite data detector having first and second data detectors. The second detector of the invention starts in a known state and only runs as long as is necessary before being switched off and handing control back over to the smaller detector. Therefore, the composite data detector of the invention consumes less power than the known composite data detector and estimates bits with higher accuracy.

An audio data receiving apparatus includes a receiving unit configured to receive audio data sampled in accordance with a first clock signal; a synchronization unit configured to generate a second clock signal that is synchronized with the first clock signal by extracting clock components contained in the audio data; a demodulator configured to demodulate the audio data in accordance with the second clock signal; an oversampling unit configured to oversample the audio data demodulated by the demodulator by using a frequency higher than a frequency of the second clock signal; a clock generator configured to generate a third clock signal having a frequency nearly equal to the first clock signal; and a data output unit configured to output the audio data oversampled by the oversampling unit in accordance with the third clock signal generated by the clock generator.

Methods and systems for write compensation for optimizing the performance of a data storage or communication channel are disclosed. In one embodiment, a method comprises determining channel sensitivity to modifications in write signal parameters, detecting systematic errors in a read signal recovered from data written with a first set of write parameters, and adjusting the write signal parameters by an amount determined from the channel sensitivity such that the systematic errors are reduced when data are written with the adjusted write parameters.

A sampled amplitude read channel is disclosed for magnetic disk storage systems comprising an adaptive non-linear correction circuit for correcting non-linear distortions in the read signal, such as asymmetry caused by the non-linear response of a magneto-resistive (MR) read head. The analog read signal is sampled and the discrete time sample values equalized into a desired partial response prior to sequence detection. The non-linear correction circuit is inserted into the read path prior to the sequence detector and adaptively tuned by a least-mean-square (LMS) adaptation circuit. In one embodiment, the non-linear correction circuit is a discrete-time Volterra filter comprising a linear response for implementing an equalizing filter, and a non-linear response for attenuating non-linear distortions in the read signal. The filter coefficients of both the linear and non-linear sections of the Volterra filter are adaptively adjusted by the LMS adaptation circuit. In an alternative embodiment, the non-linear correction circuit operates in the analog domain, prior to the sampling device, where the cost and complexity can be minimized. The analog correction circuit implements an inverse response to that of the non-linearity in the read signal, and the response is adaptively tuned using an LMS update value computed in discrete-time for a Volterra filter, without actually implementing a Volterra filter. Further, the LMS update value for the analog correction circuit can be implemented using a simple squaring circuit.

A method of reading a data block from a sector of a recording media is described. The data block from the sector of the recording channel is decoded with an ECC decoder (first trial). The data block is re-decoded (second trial) using an adjusted timing recovery block that is adjusted based on the decoded data block, if the number of errors exceeded an error correction capability of the ECC decoder on the first trial. In one embodiment, the data block is reread from the same sector of the recording channel using the adjusted timing recovery block that is adjusted based on the re-decoded data block. The data block is subsequently jointly decoded with the waveforms obtained from the second trial by a possibly modified sequence detector, if the number of errors exceeded the error correction capability of the ECC decoder during the second trial.

Symbol by symbol MAP detection for signals corrupted by colored and / or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (α), backward metrics (β), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and / or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).

Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

A communications channel includes a buffer that receives user data symbols including a plurality of M-bit symbols. A seed selector receives the plurality of M-bit symbols, selectively removes symbols from a seed set based on Hamming distances between at least two of the M-bit symbols, and selects a scrambling seed from remaining symbols in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data based on the user data symbols and the scrambling seed. The communications channel is implemented in a data storage system. The seed selector ensures a minimum Hamming weight of 15 percent in the scrambled user data. The seed selector compares first and second user data symbols in the plurality of M-bit symbols.

A composite data detector having first and second data detectors. The second detector of the invention starts in a known state and only runs as long as is necessary before being switched off and handing control back over to the smaller detector. Therefore, the composite data detector of the invention consumes less power than the known composite data detector and estimates bits with higher accuracy.

A repeatable run-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values representing an RRO address mark (AM) and RRO data, and an asynchronous maximum-likelihood (AML) detector to detect the RRO AM. The AML detector selects one of either the asynchronous or interpolated sample sequences that are closest in distance to the ideal RRO AM sample sequence. In addition, a gain value is generated for each of the asynchronous and interpolated sample sequences. Once the RRO AM is detected, the AML detector provides a RRO AM found signal. Gain estimate values for either the selected asynchronous or selected interpolated sample sequences corresponding to the RRO AM found signal are averaged over a predefined number of detection events to generate a best gain error metric (BGEM). The BGEM is employed to adjust the gain of the asynchronous sample sequence.