17440 results about "Processing element" patented technology

A decodable indicia reading system can be provided for use in locating and decoding a bar code symbol represented within a frame of image data. The system can comprise a central processing unit (CPU), a memory communicatively coupled to the CPU, and two or more image sensors communicatively coupled to the CPU or to the memory. The system can be configured to select an image sensor for indicia reading by cycling through available image sensors to detect an image sensor suitable for an attempted indicia reading operation by comparing a measured parameter value to a pre-defined sensor-specific threshold value. The system can be further configured to select the first suitable or the best suitable image sensor for the attempted decodable indicia reading operation based upon the comparison result. The system can be further configured to notify the system operator which image sensor has been selected. The system can be further configured to obtain a decodable indicia image by the selected image sensor.

A computer data processing system including a central processing unit configured with a novel integrated computer control software system for the management of data objects including dynamic and automatic organization, linking, finding, cross-referencing, viewing and retrieval of multiple objects regardless of nature or source. The inventive system provides underlying component architecture having an object-oriented database structure and a metadata database structure which is unique in storing only one instance of each object while linking the object to multiple collections and domains by unique metadata links for the grouping into and retrieval from any of the collections. The system employs configurable, extensible attribute / properties of data objects in metadata format, and a truly user-friendly configurable interface that facilitates faster, more unified, comprehensive, useful and meaningful information management. Additional features include a sticky path object hierarchy viewing system, key phrase linking, viewing by reference, and drag-and-drop relationship link creation.

A method and apparatus are provided for building an intelligent automated assistant. Embodiments of the present invention rely on the concept of “active ontologies” (e.g., execution environments constructed in an ontology-like manner) to build and run applications for use by intelligent automated assistants. In one specific embodiment, a method for building an automated assistant includes interfacing a service-oriented architecture that includes a plurality of remote services to an active ontology, where the active ontology includes at least one active processing element that models a domain. At least one of the remote services is then registered for use in the domain.

A system and method for classifying and measuring human motion senses the motion of the human and the metabolism of the human. A motion classification unit determines the motion type being carried out by the human and provides the motion classification information to an energy estimator and a health monitor. The energy estimator also receives the metabolism information and therefrom provides an estimate of energy expended by the human. The health monitor triggers an alarm if health related thresholds are traversed. The motion classification is also provided to a processing unit that in turn provides the data to a Kalman filter, which has an output that is provided as feedback to the motion classification unit, the energy estimator and health monitor. Altimeter, GPS and magnetic sensors may also be provided for monitoring the human motion, and initial input and landmark input data inputs are provided to the system.

A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each processing element a first dimensional extrema for a first dimension, wherein the first dimensional extrema is related to the local extrema of the processing elements in the first dimension and wherein the first dimensional extrema has a most significant byte and a least significant byte, determining within each processing element a next dimensional extrema for a next dimension of the n-dimensional array, wherein the next dimensional extrema is related to the first dimensional extrema and wherein the next dimensional extrema has a most significant byte and a least significant byte; and repeating the determining within each processing element a next dimensional extrema for each of the n-dimensions, wherein each of the next dimensional extrema is related to a dimensional extrema from a previously selected dimension.

An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host system includes a memory controller coupling the active memory device to a host CPU and a mass storage device. The active memory device includes a command engine issuing instructions responsive to the task commands to either an array control unit or a DRAM control unit. The instructions provided to the DRAM control unit cause data to be written to or read from a DRAM and coupled to or from either the processing elements or a host / memory interface. The processing elements execute instructions provided by the array control unit to decompress data written to the DRAM through the host / memory interface and compress data read from the DRAM through the host / memory interface.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

An apparatus for providing flexible text based language identification includes an alphabet scoring element, an n-gram frequency element and a processing element. The alphabet scoring element may be configured to receive an entry in a computer readable text format and to calculate an alphabet score of the entry for each of a plurality of languages. The n-gram frequency element may be configured to calculate an n-gram frequency score of the entry for each of the plurality of languages. The processing element may be in communication with the n-gram frequency element and the alphabet scoring element. The processing element may also be configured to determine a language associated with the entry based on a combination of the alphabet score and the n-gram frequency score.

A system and method are disclosed for controlling the frequency of a common clock which is shared by a plurality of processing elements. The usage of the common clock by each of the plurality of processing elements is measured, and the common clock is controlled to have a frequency determined as a function of the measured common clock usage by the plurality of processing elements.

Systems and methods are disclosed for utilizing one or more tablet computer assemblies in a portable communications system. A tablet computer assembly includes a global positioning system module, an L-band transceiver, and a processing system. The global positioning system module that produces location information associated with the position of the tablet computer assembly. The L-band transceiver broadcasts the location information to at least one portable communication device through a relay network and receives location information from the at least one portable communications device via the relay network. The processing unit provides messages to the L-band transceiver and updates a display associated with the tablet computer assembly according the received location information and the location information produced at the global positioning system module.