A processor (100) is provided that is a programmable fixed point
digital signal processor (DSP) with variable instruction length, offering both high
code density and easy
programming. Architecture and
instruction set are optimized for low
power consumption and high efficiency execution of
DSP algorithms, such as for
wireless telephones, as well as pure control tasks. The processor includes an
instruction buffer unit (106), a program flow
control unit (108), an address / data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve
processing performance. A
memory interface unit (104) provides parallel access to data and instruction memories. The
instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the
instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed.
Bit field processing and various addressing
modes, such as
circular buffer addressing, further support execution of
DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.